HD6432621 Hitachi, HD6432621 Datasheet - Page 10

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Section
8.3.3 DTC Vector
Table
Table 8-4 Interrupt
Sources, DTC Vector
Addresses, and
Corresponding
8.3.10 Number of DTC
Execution States
9.10.2 Register
Configuration
12.2.2 Timer
Control/Status Register
(TCSR)
Bit 7—Overflow Flag
(OVF)
Page
194
203
275
402
Description
4th line changed as follows
Number of execution states = I · (S
For example, when the DTC vector address table is located in on-chip ROM,
normal mode is set, and data is transferred from the on-chip ROM to an
internal I/O register, the time required for the DTC operation is 14 states. The
time from activation to the end of the data write is 11 states.
Port F Data Register (PFDR)
Explanation added to 8th line as follows
Bit 7 in PFDR is reserved, and only 0 may be written to it.
Explanation added to 8th line as follows
In interval timer mode, to clear OVF flag in WOVI handling routine, read
TCSR when OVF = 1, then write with 0 to OVF, as stated above.
When WOVI is masked and OVF flag is poling, if contention between OVF
flag set and TCSR read is occurred, OVF = 1 is read but OVF can not be
cleared by writing with 0 to OVF.
In this case, reading TCSR when OVF = 1 two times meet the requirements
of OVF clear condition. Please read TCSR when OVF = 1 two times before
writing with 0 to OVF.
Bit
Initial value
Read/Write
TGI5A (GR5A compare
match/input capture)
TGI5B (GR5B compare
match/input capture)
Reserved
RXI0
(reception complete 0)
TXI0
(transmit data empty 0)
:
:
:
R/W
—
7
0
PF6DR
R/W
6
0
TPU
channel 5
—
SCI
channel 0 82
PF5DR
R/W
5
0
+ M · S
PF4DR
R/W
I
4
0
+ 1) +
60
61
64
65
68
69
72
73
74
75
81
M
PF3DR
R/W
3
0
H'0478
H'047A
H'0480
H'0482
H'0488
H'048A
H'0490
H'0492
H'0494
H'0496
H'04A2
H'04A4
(J · S
PF2DR
R/W
J
2
0
+ K · S
PF1DR
R/W
K
1
0
DTCED5
DTCED4
DTCED3
DTCED2
DTCED1
DTCED0
DTCEE7
DTCEE6
DTCEE5
DTCEE4
DTCEE3
DTCEE2
+ L · S
PF0DR
R/W
0
0
L
)