HD6432621 Hitachi, HD6432621 Datasheet - Page 728

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

20.4
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 1, 2, or 4. The multiplication factor is set with the STC bits in LPWRCR. The phase of
the rising edge of the internal clock is controlled so as to match that at the EXTAL pin.
When setting the multiplication factor, ensure that the clock frequency after multiplication does
not exceed the maximum operating frequency of the chip.
When the multiplication factor of the PLL circuit is changed, the operation varies according to the
setting of the STCS bit in SCKCR.
When STCS = 0 (initial value), the setting becomes valid after a transition to software standby
mode. The transition time count is performed in accordance with the setting of bits STS2 to STS0
in SBYCR.
[1] The initial PLL circuit multiplication factor is 1.
[2] A value is set in bits STS2 to STS0 to give the specified transition time.
[3] The target value is set in STC1 and STC0, and a transition is made to software standby mode.
[4] The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.
[5] Software standby mode is cleared, and a transition time is secured in accordance with the
[6] After the set transition time has elapsed, the LSI resumes operation using the target
If a PC break is set for the SLEEP instruction that causes a transition to software standby mode in
[3], software standby mode is entered and break exception handling is executed after the
oscillation stabilization time. In this case, the instruction following the SLEEP instruction is
executed after execution of the RTE instruction.
When STCS = 1, the LSI operates on the changed multiplication factor immediately after bits
STC1 and STC0 are rewritten.
20.5
The medium-speed clock divider divides the system clock to generate ø/2, ø/4, ø/8, ø/16, and ø/32.
20.6
The bus master clock selection circuit selects the system clock (ø) or one of the medium-speed
clocks (ø/2, ø/4, ø/8, ø/16, and ø/32) to be supplied to the bus master, according to the settings of
the SCK2 to SCK0 bits in SCKCR.
684
setting in STS2 to STS0.
multiplication factor.
PLL Circuit
Medium-Speed Clock Divider
Bus Master Clock Selection Circuit