HD6432621 Hitachi, HD6432621 Datasheet - Page 350

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
Channel
3
Note:
306
*1 When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this
Bit 3
IOC3
0
1
setting is invalid and input capture/output compare is not generated.
Bit 2
IOC2
0
1
0
1
Bit 1
IOC1
0
1
0
1
0
1
*
Bit 0
IOC0
0
1
0
1
0
1
0
1
0
1
*
*
Description
TGR3C
is output
compare
register*
TGR3C
is input
capture
register*
1
1
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCC3 pin
Capture input
source is channel
4/count clock
0 output at compare match
1 output at compare match
Toggle output at compare
match
0 output at compare match
1 output at compare match
Toggle output at compare
match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4
count-up/count-down
(Initial value)
*: Don’t care

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