HD6432646 Hitachi, HD6432646 Datasheet - Page 1092

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Notes: *1 TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,
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*2 RXI and ERI interrupt request cancellation can be performed by reading 1 from the
*3 The TDRE flag in SSR is fixed at 1.
*4 In this state, serial transmission is started when transmit data is written to TDR and the
*5 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
*6 Serial reception is started in this state when a start bit is detected in asynchronous
*7 When receive data including MPB = 0 is received, receive data transfer from RSR to
*8 TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then
*9 Outputs a clock of the same frequency as the bit rate.
*10 Inputs a clock with a frequency 16 times the bit rate.
then clearing it to 0, or clearing the TIE bit to 0.
RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the
RIE bit to 0.
TDRE flag in SSR is cleared to 0.
SMR setting must be performed to decide the transfer format before setting the TE bit
to 1.
retain their states.
mode or serial clock input is detected in clocked synchronous mode.
SMR setting must be performed to decide the transfer format before setting the RE bit
to 1.
RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR ,
is not performed. When receive data including MPB = 1 is received, the MPB bit in
SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and
ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER
flag setting is enabled.
clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.