HD6432646 Hitachi, HD6432646 Datasheet - Page 491

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV
bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the
O/E bit in SMR.
Bit 2
SINV
0
1
Bit 1—Reserved: It is always read as 1 and cannot be modified.
Bit 0—Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a
normal SCI, 0 should be written in this bit.
Bit 0
SMIF
0
1
13.2.10 Module Stop Control Register B (MSTPCRB)
MSTPCRB is an 8-bit readable/writable register that perform module stop mode control.
Setting any of bits MSTPB7 to MSTPB6 to 1 stops SCI0 to SCI1 operating and enter module stop
mode on completion of the bus cycle. For details, see section 22.5, Module Stop Mode.
MSTPCRB is initialized to H'FF by a reset and in hardware standby mode. They are not
initialized in software standby mode.
Bit
Initial value
R/W
Description
TDR contents are transmitted without modification
Receive data is stored in RDR without modification
TDR contents are inverted before being transmitted
Receive data is stored in RDR in inverted form
Description
Operates as normal SCI (smart card interface function disabled)
Smart card interface function enabled
:
:
:
MSTPB7
R/W
7
1
MSTPB6
R/W
6
1
MSTPB5
R/W
5
1
MSTPB4
R/W
4
1
MSTPB3
R/W
3
1
MSTPB2
R/W
2
1
MSTPB1
R/W
1
1
(Initial value)
(Initial value)
MSTPB0
R/W
0
1
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