HD6432646 Hitachi, HD6432646 Datasheet - Page 339

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter
clearing source.
Channel
0, 3
Channel
1, 2, 4, 5
Notes: *1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
*2 When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
*3 Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
buffer register setting has priority, and compare match/input capture does not occur.
modified.
Bit 7
CCLR2
0
1
Bit 7
Reserved
0
* 3
Bit 6
CCLR1
0
1
0
1
Bit 6
CCLR1
0
1
Bit 5
CCLR0
0
1
0
1
0
1
0
1
Bit 5
CCLR0
0
1
0
1
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
capture
TCNT cleared by TGRD compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation
* 2
* 2
* 1
* 1
* 1
(Initial value)
(Initial value)
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