24LC256 MicrochipTechnology, 24LC256 Datasheet

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24LC256

Manufacturer Part Number
24LC256
Description
256KI2CCMOSSerialEEPROM
Manufacturer
MicrochipTechnology
Datasheet
M
256K I
DEVICE SELECTION TABLE
Part
V
Max Clock
CC
Number
Range
Frequency
24AA256
1.8-5.5V
400 kHz
24LC256
2.5-5.5V
400 kHz
100 kHz for V
< 2.5V.
CC
100 kHz for E temperature range.
FEATURES
• Low power CMOS technology
- Maximum write current 3 mA at 5.5V
- Maximum read current 400 A at 5.5V
- Standby current 100 nA typical at 5.5V
• 2-wire serial interface bus, I
2
C compatible
• Cascadable for up to eight devices
• Self-timed ERASE/WRITE cycle
• 64-byte page-write mode available
• 5 ms max write-cycle time
• Hardware write protect for entire array
• Schmitt trigger inputs for noise suppression
• 100,000 erase/write cycles guaranteed
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC (208 mil) packages
• Temperature ranges:
- Industrial (I):
-40 C to
- Automotive (E):
-40 C to +125 C
DESCRIPTION
The Microchip Technology Inc. 24AA256/24LC256
(24xx256*) is a 32K x 8 (256K bit) Serial Electrically
Erasable PROM, capable of operation across a broad
voltage range (1.8V to 5.5V). It has been developed for
advanced, low power applications such as personal
communications or data acquisition. This device also
has a page-write capability of up to 64 bytes of data.
This device is capable of both random and sequential
reads up to the 256K boundary. Functional address
lines allow up to eight devices on the same bus, for up
to 2 Mbit address space. This device is available in the
standard 8-pin plastic DIP, and 8-pin SOIC (208 mil)
packages.
2
I
C is a trademark of Philips Corporation.
*24xx256 is used in this document as a generic part number for the 24AA256/24LC256 devices.
1998 Microchip Technology Inc.
24AA256/24LC256
2
C
CMOS Serial EEPROM
PACKAGE TYPE
PDIP
Temp
Ranges
I
I, E
SOIC
BLOCK DIAGRAM
A0…A2
I/O
CONTROL
+85 C
LOGIC
I/O
SCL
SDA
V
CC
V
SS
A0
1
8
Vcc
A1
2
7
WP
A2
3
6
SCL
Vss
4
5
SDA
8
1
A0
V
CC
7
2
WP
A1
6
SCL
3
A2
5
SDA
V
4
SS
WP
HV GENERATOR
MEMORY
EEPROM
CONTROL
XDEC
ARRAY
LOGIC
PAGE LATCHES
YDEC
SENSE AMP
R/W CONTROL
DS21203C-page 1

Related parts for 24LC256

24LC256 Summary of contents

Page 1

... Mbit address space. This device is available in the standard 8-pin plastic DIP, and 8-pin SOIC (208 mil) packages trademark of Philips Corporation. *24xx256 is used in this document as a generic part number for the 24AA256/24LC256 devices. 1998 Microchip Technology Inc. 24AA256/24LC256 2 ™ C ...

Page 2

... T SP SDA OUT WP DS21203C-page 2 TABLE 1-1 Name A0, A1, A2 User Configurable Chip Selects V Ground SS +1.0V CC SDA Serial Data SCL Serial Clock WP Write Protect Input +1.8 to 5.5V (24AA256) CC +2.5 to 5.5V (24LC256 +1. +4.5V to 5.5V CC Symbol Min Max Units V 0.7 V — — 0.05 V — ...

Page 3

... This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip’s BBS or website. 1998 Microchip Technology Inc. 24AA256/24LC256 V = +1.8V to 5.5V Tamb = - + ...

Page 4

... PIN DESCRIPTIONS 2.1 A0, A1, A2 Chip Address Inputs The A0, A1, A2 inputs are used by the 24xx256 for multiple device operation. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true eight devices may be connected to the same bus by using different chip select bit combinations ...

Page 5

... SCL SDA Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. 1998 Microchip Technology Inc. 24AA256/24LC256 (D) (D) ADDRESS OR DATA ALLOWED VALID TO CHANGE Acknowledge Bit ...

Page 6

... DEVICE ADDRESSING A control byte is the first byte received following the start condition from the master device (Figure 5-1). The control byte consists of a 4-bit control code; for the 24xx256 this is set as 1010 binary for read and write operations. The next three bits of the control byte are the chip select bits (A2, A1, A0) ...

Page 7

... A C BUS ACTIVITY don’t care bit 1998 Microchip Technology Inc. 24AA256/24LC256 6.2 Page Write The write control byte, word address, and the first data byte are transmitted to the 24xx256 in the same way byte write. But instead of generating a stop condi- ...

Page 8

... ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (This feature can be used to maximize bus throughput.) Once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle ...

Page 9

... SDA LINE BUS ACTIVITY 1998 Microchip Technology Inc. 24AA256/24LC256 8.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24xx256 as part of a write operation (R/W bit set to 0) ...

Page 10

... NOTES: DS21203C-page 10 1998 Microchip Technology Inc. ...

Page 11

... SM = Plastic SOIC (208 mil Body, EIAJ standard), 8-lead -125 C 2 24AA256 256K bit 1. Serial EEPROM 2 24AA256T 256K bit 1. Serial EEPROM (Tape and Reel) 2 24LC256 256K bit 2. Serial EEPROM 2 24LC256T 256K bit 2. Serial EEPROM (Tape and Reel) DS21203C-page 11 ...

Page 12

M W ORLDWIDE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: ...

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