HIP6500CB Intersil Corporation, HIP6500CB Datasheet
HIP6500CB
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HIP6500CB Summary of contents
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... S0 and CLK S1/S2, and uses the 3V3 pin as input source for its internal pass element. Ordering Information TEMP. o PART NUMBER RANGE ( C) PACKAGE HIP6500CB SOIC HIP6500EVAL1 Evaluation Board 1 December 1999 Features • Provides 5 ACPI-Controlled Voltages - 5V Active/Sleep (5V - 3.3V Active/Sleep (3. ...
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Block Diagram 12V 12V MONITOR 10.2V/9.2V TO 5VSB EA3 + - TO UV 3V3SB DETECTOR FAULT/MSEL UV DETECTOR TO 5VSB COMPARATOR 3.75V - 5VDL GND 3V3DL 5V 3V3 3V3DLSB 5VSB 5VSB POR EA4 - ...
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Simplified Power System Diagram +5V IN +12V IN +5V SB +3. 3.3V DUAL 3.3V FAULT/MSEL SHUTDOWN SX 2 ENXVDL 2 Typical Application +5V IN +12V IN +5V SB +3. OUT1 3. OUT1 ...
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Absolute Maximum Ratings Supply Voltage +7.0V 5VSB 12V. . ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued) PARAMETER 3.3V LINEAR REGULATOR (V DUAL OUT3 Sleep State Regulation 3V3DL Nominal Voltage Level 3V3DL Undervoltage Rising Threshold 3V3DL Undervoltage Hysteresis 3V3DLSB Output Drive ...
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Functional Pin Description 3V3 (Pin 7) Connect this pin to the ATX 3.3V output. This pin provides the output current for the 2V5CLK pin, and is monitored for power quality. 5VSB (Pin 2) Provide a very well de-coupled 5V bias ...
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This pin is the output of the internal 3. This internal regulator operates continuously for as OUT1 long as the 5VSB bias voltage is applied to the HIP6500. This pin is monitored for under-voltage events. ...
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Functional Timing Diagrams Figures 4 through 8 are timing diagrams, detailing the power up/down sequences of all three outputs in response to the status of the enable (EN3VDL, EN5VDL) and sleep-state pins (S3, S5), as well as the status of ...
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S3 S5 12V INTERNAL VSEN2 DEVICE DRV2 VSEN2 3V3SB VCLK FIGURE 8. 2.5/3.3V , 3.3V AND VCLK TIMING DIAGRAM MEM SB Soft-Start Circuit SOFT-START INTO SLEEP STATES (S3, S4/S5) The 5VSB POR function initiates the soft-start sequence. An internal ...
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SOFT-START INTO ACTIVE STATES (S0, S1) If both S3 and S5 are logic high at the time the 5VSB is applied, the HIP6500 will assume active state wake-up and keep off the controlled external transistors and the VCLK output until ...
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Application Guidelines Soft-Start Interval The 5VSB output of a typical ATX supply is capable of 725mA. During power- sleep state, it needs to provide sufficient current to charge up all the output capacitors and simultaneously provide some amount ...
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IN + 5VSB 12V 12V 5VSB SS 5VDLSB HF1 5VDL C BULK1 3V3SB V OUT1 Q2 3V3DLSB C HIP6500 HF3 V OUT3 3V3DL DLA C 5V BULK3 VCLK VSEN2 Q3 DRV2 3V3 ...
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At the transition between active and sleep states, this phenomena could result in the 5VSB voltage dropping below the POR level (typically 4.1V) and temporarily disabling the HIP6500. The solution to a potential problem such as this ...
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... MMBT2907AL. For detailed information on the circuit, including a Bill-of-Materials and circuit board description the see Application Note AN9862. OUT3 ), the 2.5V OUT2 CLK Also see Intersil Corporation’s web page voltage (V ) OUT5 (http://www.intersil.com) or Intersil AnswerFAX (321-724-7800) for the latest information 12V ...
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... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...