HIP6502BCB Intersil Corporation, HIP6502BCB Datasheet - Page 10

• Manufacturer Part Number: HIP6502BCB
• Description: Multiple Linear Power Controller with ACPI Control Interface
• Manufacturer: Intersil Corporation

takes place. Operation resumes at 140
temperature cycling occurs until the fault-causing condition
is removed.
In HIP6502B applications, loss of any one active ATX output
(3.3V
voltage monitors) during active state operation causes the
chip to switch to S5 sleep state, in addition to reporting the
input UV condition on the FAULT/MSEL pin. Exiting from this
forced-S5 state can only be achieved by returning the
faulting input voltage above its UV threshold, by resetting the
chip through removal of 5V
the SS pin at a potential lower than 0.8V.
Output Voltages
The output voltages are internally set and do not require any
external components. Selection of the memory voltages is
done by means the MSEL pin. Leaving the MSEL pin floating
enables support of both memory outputs. Pulling the MSEL
pin below 0.9V enables support only for the 2.5V
output. It is important to notice that in a typical application
(such as that presented in Figure 3), setting the MSEL low
will not prevent the 3.3V
state. Pulling the MSEL pin above 2.9V enables 3.3V
output support, only. Following every 3.3V
reset (see Soft-Start Circuit), or at the exit from an S4/S5
sleep state, the MSEL setting is latched in. During active
state (S0/S1/S2) and S3 sleep state, any changes in MSEL
status are ignored.
Application Guidelines
Soft-Start Interval
The 5VSB output of a typical ATX supply is capable of
725mA. During power-up in a sleep state, it needs to provide
sufficient current to charge up all the output capacitors and
simultaneously provide some amount of current to the output
loads. Drawing excessive amounts of current from the 5VSB
output of the ATX can lead to voltage collapse and induce a
pattern of consecutive restarts with unknown effects on the
system’s behavior or health.
The built-in soft-start circuitry allows tight control of the slew-
up speed of the output voltages controlled by the HIP6502B,
thus enabling power-ups free of supply drop-off events.
Since the outputs are ramped up in a linear fashion, the
current dedicated to charging the output capacitors can be
calculated with the following formula:
I
C
V
capacitance and the voltage of an output (total charge
delivered to all outputs)
I
SS
COUT
SS
BG
C
- soft-start current (typically 10 A)
OUT
- soft-start capacitor
- bandgap voltage (typically 1.26V)
IN
=
, 5V
x V
----------------------------- -
C
SS
IN
OUT
I
SS
, or 12V
V
) - sum of the products between the
BG
IN
MEM
; as detected by the on-board
C
OUT
SB
10
from being operational in active
bias voltage, or by bringing
V
OUT
o
, where
C and the
SB
ramp-up, chip
MEM
MEM
HIP6502B
Due to the various system timing events, it is recommended
that the soft-start interval not be set to exceed 30ms.
Shutdown
In case of a FAULT condition that might endanger the
computer system, or at any other time, all the HIP6502B
outputs can be shut down by pulling the SS pin below the
specified shutdown level (typically 0.8V) with an open drain
or open collector device capable of sinking a minimum of
2mA. Pulling the SS pin low effectively shuts down all the
pass elements. Upon release of the SS pin, the HIP6502B
undergoes a new soft-start cycle and resumes normal
operation in accordance to the ATX supply and control pins
status.
Layout Considerations
The typical application employing a HIP6502B is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical by-pass
current.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, closer to the memory
load if possible, but not excessively far from the clock chip or
the processor. Insure the VSEN1 and VSEN2 connections
are properly sized to carry 250mA without significant
resistive losses; similar guideline applies to the VCLK
output, which can deliver as much as 800mA (typical). As
the current for the VCLK output is provided from the ATX
3.3V, the connection from the 3V3 pin to the 3.3V plane
should be sized to carry the maximum clock output current
while exhibiting negligible voltage losses. Similarly, the 5VSB
pin and the 5V pin are carrying significant levels of current -
for best results, insure these pins are connected to their
respective sources through adequate traces. The pass
transistors should be placed on pads capable of heatsinking
matching the device’s power dissipation. Where applicable,
multiple via connections to a large internal plane can
significantly lower localized device temperature rise.
Placement of the decoupling and bulk capacitors should
follow a placement reflecting their purpose. As such, the
high-frequency decoupling capacitors should be placed as
close as possible to the load they are decoupling; the ones
decoupling the controller close to the controller pins, the
ones decoupling the load close to the load connector or the
load itself (if embedded). Even though bulk capacitance
(aluminum electrolytics or tantalum capacitors) placement is
not as critical as the high-frequency capacitor placement,
having these capacitors close to the load they serve is
preferable.
The only critical small signal component is the soft-start
capacitor, C
control IC and connect to ground through a via placed close
SS
. Locate this component close to SS pin of the