RG82845M Intel, RG82845M Datasheet - Page 19

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

1.7.
250687-002
Table 3. MCH-M Clock Ratio Table
R
System Interrupts
The Intel 845MP/845MZ Chipset MCH-M supports both 8259 and Intel Mobile Pentium 4 Processor-M
interrupt delivery mechanisms. The serial APIC interrupt mechanism is not supported.
The 8259 support consists of flushing inbound hub interface write buffers when an Interrupt
Acknowledge cycle is forwarded from the system bus to the hub interface.
The Intel 845MP/845MZ Chipset MCH-M supports the Mobile Intel Pentium 4 Processor-M interrupt
delivery mechanism. PCI MSI interrupts are generated as Memory Writes. The MCH-M decodes
upstream Memory Writes to the range 0FEE0_0000h - 0FEEF_FFFFh from AGP and the hub interface
as message based interrupts. The MCH-M forwards the Memory Writes, along with the associated write
data, to the system bus as an Interrupt Message transaction. Note that since this address does not decode
as part of main memory, the write cycle and the write data does not get forwarded to DRAM via the write
buffer. The Intel 845MP/845MZ Chipset MCH-M provides the response and TRDY# for all Interrupt
Message cycles including the ones originating from the MCH-M. The Intel 845MP/845MZ Chipset
MCH-M supports interrupt re-direction for inter-processor interrupts (IPIs) as well as upstream interrupt
memory writes.
For message based interrupts, system write buffer coherency is maintained by relying on strict ordering
of Memory Writes. The Intel 845MP/845MZ Chipset MCH-M ensures that all Memory Writes received
from a given interface prior to an interrupt message Memory Write are delivered to the system bus for
snooping in the same order that they occur on the given interface.
System Memory
Hub interface
Interface
AGP
DDR 200 MHz
Datasheet
66 MHz
66 MHz
Speed
Intel
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
CPU System Bus Frequency Ratio
1:1 synchronous
Asynchronous
Asynchronous
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