RG82845M Intel, RG82845M Datasheet - Page 62

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

Intel
62
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
6:4
3:0
Bit
Reserved
Mode Select (SMS). These bits select the special operational mode of the DRAM interface. The
special modes are intended for initialization at power up.
000: Post Reset state – When the MCH-M exits reset (power-up or otherwise), the mode select field
is cleared to “000”.
During any reset sequence, while power is applied and reset is active, the MCH-M asserts all CKE
signals. After internal reset is de-asserted, CKE signals remain de-asserted until this field is written to
a value different than “000”. On this event, all CKE signals are asserted.
During suspend, MCH-M internal signal triggers DRAM controller to flush pending commands and
enter all rows into Self-Refresh mode. As part of resume sequence, MCH-M will be reset – which will
clear this bit field to “000” and maintain CKE signals de-asserted. After internal reset is de-asserted,
CKE signals remain de-asserted until this field is written to a value different than “000”. On this event,
all CKE signals are asserted.
During entry to other low power states (C3, S1M), MCH-M internal signal triggers DRAM controller to
flush pending commands and enter all rows into Self-Refresh mode. During exit to normal mode,
MCH-M signal triggers DRAM controller to exit Self-Refresh and resume normal operation without
S/W involvement.
001: NOP Command Enable – All CPU cycles to DRAM result in a NOP command on the DRAM
interface.
010: All Banks Pre-charge Enable – All CPU cycles to DRAM result in an “all banks precharge”
command on the DRAM interface.
011: Mode Register Set Enable – All CPU cycles to DRAM result in a “mode register” set command
on the DRAM interface. Host address lines are mapped to memory address lines in order to specify
the command sent. Host address lines [15:3] are mapped to MA[12:0].
100: Extended Mode Register Set Enable – All processor cycles to SDRAM result in an “extended
mode register set” command on the DRAM interface (DDR only). Host address lines are mapped to
DDR address lines in order to specify the command sent. Host address lines [15:3] are mapped to
MA[12:0].
101: Reserved
110: CBR Refresh Enable – In this mode all CPU cycles to DRAM result in a CBR cycle on the DDR
interface
111: Normal operation
Datasheet
Description
250687-002
R