K6R1008C1B- Samsung semiconductor, K6R1008C1B- Datasheet

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K6R1008C1B-

Manufacturer Part Number
K6R1008C1B-
Description
128Kx8 Bit High Speed Static RAM5V Operating/ Revolutionary Pin out. Operated at Commercial and Industrial Temperature Ranges.
Manufacturer
Samsung semiconductor
Datasheet
Document Title
K6R1008C1B-C, K6R1008C1B-I
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
128Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Ranges.
Rev No.
Rev. 0.0
Rev.1.0
Rev.2.0
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary.
Release to Final Data Sheet.
2.1. Delete Preliminary.
2.2. Delete 32-SOJ-300 package.
2.3. Delete L-version.
2.4. Delete Data Retention Characteristics and Waveform.
2.5. Add Capacitive load of the test environment in A.C test load.
2.6. Change D.C characteristics.
Items
I
I
CC
SB
(8/10/12ns part)
160/150/140mA
Previous spec.
30mA
- 1 -
(8/10/12ns part)
160/155/150mA
Changed spec.
50mA
Apr. 1st, 1997
Jun. 1st, 1997
Feb. 25th, 1998
Draft Data
CMOS SRAM
PRELIMINARY
Preliminary
PRELIMINARY
PRELIMINARY
February 1998
Design Target
Preliminary
Final
Remark
Rev 2.0

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K6R1008C1B- Summary of contents

Page 1

... K6R1008C1B-C, K6R1008C1B-I Document Title 128Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial and Industrial Temperature Ranges. Revision History Rev No. History Rev. 0.0 Initial release with Design Target. Rev.1.0 Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary. Rev.2.0 Release to Final Data Sheet. ...

Page 2

... TTL Compatible Inputs and Outputs • I/O Compatible with 3.3V Device • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Center Power/Ground Pin Configuration • Standard Pin Configuration K6R1008C1B-J : 32-SOJ-400 K6R1008C1B-T: 32-TSOP2-400CF FUNCTIONAL BLOCK DIAGRAM Clk Gen. Pre-Charge Circuit A 0 ...

Page 3

... K6R1008C1B-C, K6R1008C1B-I ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative Voltage on V Supply Relative Power Dissipation Storage Temperature Operating Temperature Commercial Industrial * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...

Page 4

... K6R1008C1B-C, K6R1008C1B-I AC CHARACTERISTICS ( TEST CONDITIONS* Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads * bove test conditions are also applied at industrial temperature range. The a Output Loads( OUT ...

Page 5

... K6R1008C1B-C, K6R1008C1B-I WRITE CYCLE* Parameter Symbol Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width (OE High) Write Pulse Width (OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z * The above parameters are also guaranteed at industrial temperature range ...

Page 6

... K6R1008C1B-C, K6R1008C1B-I NOTES(READ CYCLE high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address and t are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V ...

Page 7

... K6R1008C1B-C, K6R1008C1B-I TIMING WAVEFORM OF WRITE CYCLE(3) Address CS WE High-Z Data in High-Z Data out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; ...

Page 8

... K6R1008C1B-C, K6R1008C1B-I PACKAGE DIMENSIONS 32-SOJ-400 #32 11.18 0.12 0.440 0.005 #1 +0.10 0.43 -0.05 0. +0.004 0.017 0.0375 -0.002 32-TSOP2-400CF #32 #1 21.35 0.841 20.95 0.825 0.95 0. 0.10 0.037 0.016 0.004 #17 #16 21.36 MAX 0.841 20.95 0.12 0.825 0.005 1.30 ( 0.051 1.30 ( 0.051 +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 #17 11.76 0.20 0.463 0.008 #16 MAX 0.10 0.004 1.00 0.10 0.039 0.047 0.004 1.27 0.05 MIN 0.050 0.002 - 8 - PRELIMINARY PRELIMINARY ...

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