K6T4016U3C Samsung semiconductor, K6T4016U3C Datasheet - Page 8

• Manufacturer Part Number: K6T4016U3C
• Description: 256Kx16 bit Low Power and Low Voltage CMOS Static RAM
• Manufacturer: Samsung semiconductor

DATA RETENTION WAVE FORM
K6T4016V3C, K6T4016U3C Family
CS controlled
TIMING WAVEFORM OF WRITE CYCLE(3)
1. 3.0V for K6T4016V3C Family, 2.7V for K6T4016U3C Family
Address
CS
UB, LB
WE
Data in
Data out
NOTES (WRITE CYCLE)
1. A wri
2. t
3. t
4. t
V
3.0/2.7V
2.2V
V
CS
GND
CC
DR
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The t
CW
AS
WR
is measured from the address valid to the beginning of write.
is measured from the CS going low to the end of write.
is measured from the end of write to the address change. t
t
e occurs during the overlap(t
1)
WP
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
High-Z
t
SDR
t
AS(3)
WP
(UB, LB Controlled)
is measured from the beginning of write to the end of write.
WR
Data Retention Mode
is applied in case a write ends with CS or WE going high.
CS V
8
t
t
AW
CW(2)
t
WC
t
BW
t
CC
WP(1)
- 0.2V
t
DW
Data Valid
t
WR(4)
t
DH
High-Z
t
RDR
CMOS SRAM
Revision 2.01
October 2001