GS816218B GSI [GSI Technology], GS816218B Datasheet

GS816218B

Manufacturer Part Number

GS816218B

Description

1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs

Manufacturer

GSI [GSI Technology]

Datasheet

1.GS816218B.pdf (41 pages)

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119-, 165-, & 209-Bump BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V or 3.3 V +10%/–10% core power supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-, 165-, and 209-bump BGA package

Functional Description

Applications

The GS816218(B/D)/GS816236(B/D)/GS816272(C) is an

18,874,368-bit high performance synchronous SRAM with a 2-bit

burst address counter. Although of a type originally developed for

Level 2 Cache applications supporting high performance CPUs,

the device now finds application in synchronous SRAM

applications, ranging from DSP main store to networking chip set

support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Rev: 2.17 11/2004

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Flow Through

Pipeline

3-1-1-1

2-1-1-1

3.3 V

Curr (x18)

Curr (x36)

Curr (x72)

Curr (x18)

Curr (x36)

Curr (x72)

tCycle

1M x 18, 512K x 36, 256K x 72

18Mb Sync Burst SRAMs

Parameter Synopsis

-250

280

330

175

200

2.5

4.0

n/a

5.5

n/a

1/41

-225

255

300

165

190

2.7

4.4

n/a

6.0

n/a

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

SCD and DCD Pipelined Reads

The GS816218(B/D)/GS816236(B/D)/GS816272(C) is a SCD

(Single Cycle Deselect) and DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. DCD SRAMs pipeline disable

commands to the same degree as read commands. SCD SRAMs

pipeline deselect commands one stage less than read commands.

SCD RAMs begin turning off their outputs immediately after the

deselect command has been captured in the input registers. DCD

RAMs hold the deselect command for one full cycle and then

begin turning off their outputs just after the second rising edge of

clock. The user may configure this SRAM for either mode of

operation using the SCD mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

Core and Interface Voltages

The GS816218(B/D)/GS816236(B/D)/GS816272(C) operates on

a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V

compatible. Separate output power (V

decouple output noise from the internal circuits and are 3.3 V and

2.5 V compatible.

GS816218(B/D)/GS816236(B/D)/GS816272(C)

-200

230

270

350

160

180

225

3.0

5.0

6.5

-166

200

230

300

150

170

115

3.4

6.0

7.0

-150

185

215

270

145

165

210

3.8

6.7

7.5

-133

165

190

245

135

150

185

4.0

7.5

8.5

DDQ

) pins are used to

250 MHz–133 MHz

2.5 V or 3.3 V V

Unit

2.5 V or 3.3 V I/O

Related parts for GS816218B

GS816218B Summary of contents

Page 1

BGA Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable • IEEE 1149.1 JTAG-compatible Boundary Scan ...

Page 2

GS816272 Pad Out—209 Bump BGA—Top View (Package DQG DQG A B DQG DQG BC C DQG DQG BH D DQG DQG V E DQPG DQPC V DDQ F DQC DQC V G DQC DQC V ...

Page 3

GS816272 BGA Pin Description Symbol Type I ...

Page 4

BGA—x18 Commom I/O—Top View (Package DDQ D NC DQB V DDQ E NC DQB V DDQ F NC DQB V DDQ G NC ...

Page 5

BGA—x36 Common I/O—Top View (Package DQC NC V DDQ D DQC DQC V DDQ E DQC DQC V DDQ F DQC DQC V DDQ G DQC ...

Page 6

GS816236 Pad Out—119-Bump BGA—Top View (Package Rev: 2.17 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 7

GS816218 Pad Out—119-Bump BGA—Top View (Package BPR1999.05.18 Rev: 2.17 11/2004 Specifications cited are subject to change without notice. For latest documentation see ...

Page 8

GS816218/36 BGA Pin Description Symbol Type I — ...

Page 9

Register A0– LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version shown for simplicity. Rev: 2.17 11/2004 Specifications ...

Page 10

Register A0– LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version shown for simplicity. Rev: 2.17 11/2004 Specifications ...

Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Single/Dual Cycle Deselect Control FLXDrive Output Impedance Control 9th Bit Enable Note: There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down ...

Page 12

Byte Write Truth Table Function GW Read H Read H Write byte a H Write byte b H Write byte c H Write byte d H Write all bytes H Write all bytes L Notes: 1. All byte outputs are ...

Page 13

Synchronous Truth Table Operation Address Used Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, ...

Page 14

Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B that ADSP is tied ...

Page 15

Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles ...

Page 16

Absolute Maximum Ratings (All voltages reference Symbol DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O Pin OUT P ...

Page 17

V Range Logic Levels DDQ3 Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the ...

Page 18

Undershoot Measurement and Timing 50% V – 2 50% tKC Capacitance 2 Parameter Input Capacitance Input/Output Capacitance Note: ...

Page 19

DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT, SCD, ZQ Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Rev: 2.17 11/2004 Specifications cited are subject to change without ...

Page 20

Rev: 2.17 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816218(B/D)/GS816236(B/D)/GS816272(C) 20/41 © 1999, GSI Technology ...

Page 21

AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock ...

Page 22

Begin Read A Cont Single Read Single Read CK ADSP tS tH ADSC tS ADV tS tH A0– Ba– tOE DQa–DQd Rev: 2.17 11/2004 Specifications cited ...

Page 23

Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tS tH ADV tS tH A0– Ba– and E3 only sampled with ADSC tOE ...

Page 24

Begin Read A Cont CK ADSP tS tH ADSC tS ADV tS tH Ao– Ba– tOE DQa–DQd Hi-Z Rev: 2.17 11/2004 Specifications cited are subject ...

Page 25

Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tH tS ADV tS tH Ao– Ba– and E3 only sampled with ADSP and ADSC ...

Page 26

Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, ...

Page 27

JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with ...

Page 28

Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when ...

Page 29

ID Register Contents Die Revision Code Bit # x72 ...

Page 30

Test Logic Reset 1 0 Run Test Idle 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to ...

Page 31

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the ...

Page 32

JTAG Port Recommended Operating Conditions and DC Characteristics Parameter 3.3 V Test Port Input High Voltage 3.3 V Test Port Input Low Voltage 2.5 V Test Port Input High Voltage 2.5 V Test Port Input Low Voltage TMS, TCK and ...

Page 33

TCK TDI TMS TDO Parallel SRAM input JTAG Port AC Electrical Characteristics Parameter Symbol TCK Cycle Time tTKC TCK Low to TDO Valid tTKQ TCK High Pulse Width tTKH TCK Low Pulse Width tTKL TDI & TMS Set Up Time ...

Page 34

Body, 1.0 mm Bump Pitch Bump Array A aaa e Symbol Min Typ A — — A1 0.40 0.50 ∅b 0.50 0.60 c 0.31 0.36 D 21.9 22.0 Rev 1.0 Rev: 2.17 ...

Page 35

Package Dimensions—165-Bump FPBGA (Package D; Variation 1) A1 TOP SEATING C Rev: 2.17 11/2004 Specifications ...

Page 36

Package Dimensions—119-Bump FPBGA (Package B, Variation 2 A1 TOP VIEW SEATING PLANE C Rev: 2.17 11/2004 ...

Page 37

... Ordering Information for GSI Synchronous Burst RAMs 1 Org Part Number GS816218B-250 GS816218B-225 GS816218B-200 GS816218B-166 GS816218B-150 GS816218B-133 512K x 36 GS816236B-250 512K x 36 GS816236B-225 512K x 36 GS816236B-200 512K x 36 GS816236B-166 512K x 36 GS816236B-150 512K x 36 GS816236B-133 ...

Page 38

... GS816272C-200 256K x 72 GS816272C-166 256K x 72 GS816272C-150 256K x 72 GS816272C-133 GS816218B-250I GS816218B-225I GS816218B-200I GS816218B-166I GS816218B-150I GS816218B-133I 512K x 36 GS816236B-250I 512K x 36 GS816236B-225I 512K x 36 GS816236B-200I 512K x 36 GS816236B-166I 512K x 36 GS816236B-150I 512K x 36 GS816236B-133I ...

Page 39

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New GS816218B-150IB 1.00 9/ 1999A;GS816218B-150IB 2.00 1/1999B GS816218B 2.01 1/ 2000C;GS816218 B 2.02 1/ 2000D Rev: 2 ...

Page 40

Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New GS18/362.0 1/2000DGS18/ 362.03 2/2000E GS18/362.03 2/2000E; 816218_r2_04 816218_r2_04; 816218_r2_05 816218_r2_05; 816218_r2_06 816218_r2_06; 816218_r2_07 816218_r2_07; 816218_r2_08 816218_r2_08; 816218_r2_09 816218_r2_09; 816218_r2_10 816218_r2_10; 816218_r2_11 816218_r2_11; 816218_r2_12 Rev: 2.17 11/2004 Specifications cited are subject ...

Page 41

Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New 816218_r2_12; 816218_r2_13 816218_r2_13; 816218_r2_14 816218_r2_14; 816218_r2_15 816218_r2_15; 816218_r2_16 816218_r2_16; 816218_r2_17 Rev: 2.17 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816218(B/D)/GS816236(B/D)/GS816272(C) Types of Changes ...

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