IC SHIFT REGST 8BIT PI-SO 16SOIC

74HC165D,653

Manufacturer Part Number74HC165D,653
DescriptionIC SHIFT REGST 8BIT PI-SO 16SOIC
ManufacturerNXP Semiconductors
Series74HC
74HC165D,653 datasheet
 


Specifications of 74HC165D,653

Package / Case16-SOIC (3.9mm Width)Logic TypeShift Register
FunctionParallel or Serial to SerialOutput TypeDifferential
Number Of Elements1Number Of Bits Per Element8
Voltage - Supply2 V ~ 6 VOperating Temperature-40°C ~ 125°C
Mounting TypeSurface MountCounting SequenceSerial/Parallel to Serial
Number Of Circuits1Logic FamilyHC
Propagation Delay Time16 nsSupply Voltage (max)6 V
Maximum Operating Temperature+ 125 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTSupply Voltage (min)2 V
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names568-1409-2
74HC165D-T
933713780653
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74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Rev. 03 — 14 March 2008
1. General description
The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with
JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with
complementary serial outputs (Q7 and Q7) available from the last stage. When the
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the
register asynchronously.
When PL is HIGH, data enters the register serially at the DS input and shifts one place to
the right (Q0
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the
succeeding stage.
The clock input is a gated-OR structure which allows one input to be used as an active
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE
should only take place while CP HIGH for predictable operation. Either the CP or the CE
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
2. Features
I
Asynchronous 8-bit parallel load
I
Synchronous serial input
I
Complies with JEDEC standard no. 7A
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
I
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
I
Parallel-to-serial data conversion
Q1
Q2, etc.) with each positive-going clock transition. This feature
Product data sheet

74HC165D,653 Summary of contents

  • Page 1

    Rev. 03 — 14 March 2008 1. General description The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). ...

  • Page 2

    ... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC165N +125 C 74HCT165N 74HC165D +125 C 74HCT165D 74HC165DB +125 C 74HCT165DB 74HC165PW +125 C 74HCT165PW 74HC165BQ +125 C 74HCT165BQ 5. Functional diagram Fig 1. Logic symbol 74HC_HCT165_3 Product data sheet Description DIP16 plastic dual in-line package; 16 leads (300 mil) SO16 plastic small outline package ...

  • Page 3

    ... NXP Semiconductors Fig 3. Functional diagram 6. Pinning information 6.1 Pinning 74HC165 74HCT165 GND 001aah564 Fig 4. Pin configuration (DIP16, SO16 and (T)SSOP16) 74HC_HCT165_3 Product data sheet 8-BIT SHIFT REGISTER 2 CP PARALLEL-IN/SERIAL-OUT (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input ...

  • Page 4

    ... NXP Semiconductors 6.2 Pin description Table 2. Pin description Symbol Pin GND 11, 12, 13, 14 Functional description [1] Table 3. Function table Operating modes Inputs PL parallel load L L serial shift hold “do nothing” [ HIGH voltage level HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; ...

  • Page 5

    ... NXP Semiconductors Fig 6. Timing diagram 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter V supply voltage CC I input clamping current IK I output clamping current OK I output current O I supply current ...

  • Page 6

    ... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter P total power dissipation tot [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. ...

  • Page 7

    ... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level output voltage 4.0 mA 5.2 mA LOW-level output voltage 4.0 mA 5.2 mA input leakage current supply current 6 input I capacitance 74HCT165 V HIGH-level input voltage V LOW-level ...

  • Page 8

    ... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V unless otherwise specified; for test circuit, see L Symbol Parameter Conditions 74HC165 t propagation Q7, Q7; pd delay see Figure Q7, Q7; see Q7, Q7; see transition Q7, Q7 output; see ...

  • Page 9

    ... NXP Semiconductors Table 7. Dynamic characteristics GND (ground = 0 V unless otherwise specified; for test circuit, see L Symbol Parameter Conditions t set-up time DS to CP, CE; see and CP to CE; see Figure PL; see hold time DS to CP, CE and Dn to PL; ...

  • Page 10

    ... NXP Semiconductors Table 7. Dynamic characteristics GND (ground = 0 V unless otherwise specified; for test circuit, see L Symbol Parameter Conditions 74HCT165 t propagation CE Q7, Q7; pd delay see Figure 4 5 Q7, Q7; see Q7, Q7; see transition Q7, Q7 output; see t time pulse width CP input ...

  • Page 11

    ... NXP Semiconductors Table 7. Dynamic characteristics GND (ground = 0 V unless otherwise specified; for test circuit, see L Symbol Parameter Conditions C power per package; PD dissipation V = GND capacitance [ the same as t and PHL PLH [ the same as t and THL TLH [ used to determine the dynamic power dissipation (P ...

  • Page 12

    ... NXP Semiconductors PL input CE, CP input output Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 8. The parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel load to clock (CP) and clock enable (CE) recovery time ...

  • Page 13

    ... NXP Semiconductors CP, CE input DS input CP, CE input The shaded areas indicate when the input is permitted to change for predictable output performance Measurement points are given in V and V are typical voltage output levels that occur with the output load (1) CE may change only from HIGH-to-LOW while CP is LOW, see Fig 10 ...

  • Page 14

    ... NXP Semiconductors negative positive Test data is given in Table Definitions for test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch Fig 12. Test circuit for measuring switching times Table 9. Test data Type ...

  • Page 15

    ... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

  • Page 16

    ... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

  • Page 17

    ... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 15. Package outline SOT338-1 (SSOP16) ...

  • Page 18

    ... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

  • Page 19

    ... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

  • Page 20

    ... Release date 74HC_HCT165_3 20080314 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Package SOT763-1 (DHVQFN16) added to 13 “Package • ...

  • Page 21

    ... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

  • Page 22

    ... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 14 Abbreviations ...