74HC165D-Q100

Manufacturer Part Number74HC165D-Q100
DescriptionCounter Shift Registers 8 Bit Par-Ser Out 6V
ManufacturerNXP Semiconductors
74HC165D-Q100 datasheet
 


Specifications of 74HC165D-Q100

Package / CaseSO-16Logic Family74HC
Logic TypeShift RegisterOutput TypeParallel / Serial
Propagation Delay Time250 nsMaximum Operating Temperature+ 125 C
Minimum Operating Temperature- 40 CFunction8 Bit Parallel In Serial Out
Mounting StyleSMD/SMTOperating Supply Voltage2 V to 6 V
ProductDriver ICs - VariousSupply Voltage - Max6 V
Supply Voltage - Min2 VPart # Aliases74HC165D-Q100,118
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74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
Rev. 1 — 17 July 2012
1. General description
The 74HC165-Q100; 74HCT165-Q100 are high-speed Si-gate CMOS devices that
comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky
TTL (LSTTL).
The 74HC165-Q100; 74HCT165-Q100 are 8-bit parallel-load or serial-in shift registers
with complementary serial outputs (Q7 and Q7) available from the last stage. When the
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the
register asynchronously.
When PL is HIGH, data enters the register serially at the DS input and shifts one place to
the right (Q0  Q1 Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the
succeeding stage.
The clock input is a gated-OR structure which allows one input to be used as an active
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE
should only take place while CP HIGH for predictable operation. Either the CP or the CE
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Asynchronous 8-bit parallel load
Synchronous serial input
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Applications
Parallel-to-serial data conversion
Product data sheet

74HC165D-Q100 Summary of contents

  • Page 1

    Rev. 1 — 17 July 2012 1. General description The 74HC165-Q100; 74HCT165-Q100 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). ...

  • Page 2

    ... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74HC165D-Q100 74HCT165D-Q100 40 C to +125 C 74HC165PW-Q100 74HCT165PW-Q100 40 C to +125 C 74HC165BQ-Q100 74HCT165BQ-Q100 5. Functional diagram ...

  • Page 3

    ... NXP Semiconductors Fig 3. Functional diagram 6. Pinning information 6.1 Pinning 74HC165-Q100 74HCT165-Q100 GND 8 aaa-003155 Fig 4. Pin configuration SO16 and TSSOP16 74HC_HCT165_Q100 Product data sheet 74HC165-Q100; 74HCT165-Q100 8-BIT SHIFT REGISTER ...

  • Page 4

    ... NXP Semiconductors 6.2 Pin description Table 2. Pin description Symbol Pin GND 11, 12, 13, 14 Functional description [1] Table 3. Function table Operating modes Inputs PL parallel load L L serial shift hold “do nothing” ...

  • Page 5

    ... NXP Semiconductors Fig 6. Timing diagram 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter V supply voltage CC I input clamping current IK I output clamping current ...

  • Page 6

    ... NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 10. Static characteristics Table 6. Static characteristics At recommended operating conditions ...

  • Page 7

    ... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C input I capacitance 74HCT165-Q100 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage = 20  4.0 mA ...

  • Page 8

    ... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V unless otherwise specified; for test circuit, see L Symbol Parameter Conditions 74HC165-Q100 t propagation Q7, Q7; pd delay see Figure Q7, Q7; see 4.5 V ...

  • Page 9

    ... NXP Semiconductors Table 7. Dynamic characteristics GND (ground = 0 V unless otherwise specified; for test circuit, see L Symbol Parameter Conditions t set-up time DS to CP, CE; see and CP to CE; see Figure PL; see ...

  • Page 10

    ... NXP Semiconductors Table 7. Dynamic characteristics GND (ground = 0 V unless otherwise specified; for test circuit, see L Symbol Parameter Conditions 74HCT165-Q100 t propagation CE Q7, Q7; pd delay see Figure 4 5 Q7, Q7; see Q7, Q7; see 5.0 V ...

  • Page 11

    ... NXP Semiconductors Table 7. Dynamic characteristics GND (ground = 0 V unless otherwise specified; for test circuit, see L Symbol Parameter Conditions C power per package; PD dissipation V = GND capacitance [ the same as t and PHL PLH [ the same as t and THL ...

  • Page 12

    ... NXP Semiconductors PL input CE, CP input output Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 8. Parallel load (PL) pulse width, parallel load to output (Q7 or Q7) propagation delays, parallel load to clock (CP) and clock enable (CE) recovery time ...

  • Page 13

    ... NXP Semiconductors CP, CE input DS input CP, CE input The shaded areas indicate when the input is permitted to change for predictable output performance Measurement points are given in V and V are typical voltage output levels that occur with the output load (1) CE may change only from HIGH-to-LOW while CP is LOW, see Fig 10 ...

  • Page 14

    ... NXP Semiconductors negative Test data is given in Table Definitions for test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch Fig 12. Test circuit for measuring switching times Table 9. Test data ...

  • Page 15

    ... NXP Semiconductors 13. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

  • Page 16

    ... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

  • Page 17

    ... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

  • Page 18

    ... NXP Semiconductors 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic MIL Military 15. Revision history Table 11. Revision history Document ID Release date 74HC_HCT165_Q100 v.1 20120717 74HC_HCT165_Q100 Product data sheet 74HC165-Q100 ...

  • Page 19

    ... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

  • Page 20

    ... NXP Semiconductors No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations ...

  • Page 21

    ... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Package outline ...