IC 8BIT SHIFT REGISTER 14-TSSOP

74HC164PW,112

Manufacturer Part Number74HC164PW,112
DescriptionIC 8BIT SHIFT REGISTER 14-TSSOP
ManufacturerNXP Semiconductors
Series74HC
74HC164PW,112 datasheet
 


Specifications of 74HC164PW,112

Logic TypeShift RegisterOutput TypeStandard
Number Of Elements1Number Of Bits Per Element8
FunctionSerial to ParallelVoltage - Supply2 V ~ 6 V
Operating Temperature-40°C ~ 125°CMounting TypeSurface Mount
Package / Case14-TSSOPCounting SequenceSerial to Parallel
Number Of Circuits1Logic FamilyHC
Propagation Delay Time12 nsSupply Voltage (max)6 V
Maximum Operating Temperature+ 125 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTSupply Voltage (min)2 V
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names568-4473-5
74HC164PW
74HC164PW
935187370112
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74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
Rev. 5 — 25 November 2010
1. General description
The 74HC164; 74HCT164 are high-speed Si-gate CMOS devices and are pin compatible
with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC164; 74HCT164 are 8-bit edge-triggered shift registers with serial data entry
and an output from each of the eight stages. Data is entered serially through one of two
inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry
through the other input. Both inputs must be connected together or an unused input must
be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input
and enters into Q0, which is the logical AND of the two data inputs (DSA and DSB) that
existed one set-up time prior to the rising clock edge.
A LOW level on the master reset (MR) input overrides all other inputs and clears the
register asynchronously, forcing all outputs LOW.
2. Features and benefits
Input levels:
For 74HC164: CMOS level
For 74HCT164: TTL level
Gated serial data inputs
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C.
Product data sheet

74HC164PW,112 Summary of contents

  • Page 1

    Rev. 5 — 25 November 2010 1. General description The 74HC164; 74HCT164 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with ...

  • Page 2

    ... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 40 C to +125 C 74HC164N 74HCT164N 40 C to +125 C 74HC164D 74HCT164D 40 C to +125 C 74HC164DB 74HCT164DB 40 C to +125 C 74HC164PW 74HCT164PW 40 C to +125 C 74HC164BQ 74HCT164BQ 4 ...

  • Page 3

    ... NXP Semiconductors DSA DSB FF1 Fig 4. Functional diagram 5. Pinning information 5.1 Pinning 74HC164 74HCT164 DSA 1 DSB GND 7 Fig 5. Pin configuration DIP14, SO14, (T)SSOP14 74HC_HCT164 Product data sheet FF2 FF3 FF4 001aal390 Fig 6. All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 November 2010 74HC164 ...

  • Page 4

    ... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin DSA 1 DSB 10, 11, 12, 13 GND Functional description [1] Table 3. Function table Operating Input modes MR Reset (clear) L Shift [ HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level ...

  • Page 5

    ... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter P total power dissipation tot DIP14 package SO14, (T)SSOP14 and DHVQFN14 packages [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. ...

  • Page 6

    ... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level output voltage = 20  20  20  4.0 mA 5.2 mA LOW-level output voltage = 20    4.0 mA 5.2 mA input leakage current supply current ...

  • Page 7

    ... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = ns pF; test circuit see Symbol Parameter Conditions 74HC164 t propagation CP to Qn; see pd delay HIGH to LOW MR to Qn; see PHL propagation V CC delay transition time see Figure pulse width CP HIGH or LOW; W see Figure LOW; see V CC ...

  • Page 8

    ... NXP Semiconductors Table 7. Dynamic characteristics GND = ns pF; test circuit see Symbol Parameter Conditions f maximum for Cp, see max frequency power per package; PD dissipation V = GND capacitance 74HCT164 t propagation CP to Qn; see pd delay HIGH to LOW MR to Qn; see PHL propagation V CC delay transition time see Figure 7 ...

  • Page 9

    ... NXP Semiconductors Table 7. Dynamic characteristics GND = ns pF; test circuit see Symbol Parameter Conditions C power per package; PD dissipation V = GND capacitance [ the same as t and PHL PLH [ the same as t and THL TLH [ used to determine the dynamic power dissipation (P PD  V  f   (C ...

  • Page 10

    ... NXP Semiconductors MR input CP input Qn output (1) Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 8. Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time ...

  • Page 11

    ... NXP Semiconductors Test data is given in Table Definitions test circuit termination resistance should be equal to output impedance load capacitance including jig and probe capacitance. L Fig 10. Test circuit for measuring switching times Table 9. Test data Type Input V I 74HC164 V CC 74HCT164 3.0 V 74HC_HCT164 Product data sheet ...

  • Page 12

    ... NXP Semiconductors 11. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

  • Page 13

    ... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

  • Page 14

    ... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 13. Package outline SOT337-1 (SSOP14) ...

  • Page 15

    ... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

  • Page 16

    ... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

  • Page 17

    ... NXP Semiconductors 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date 74HC_HCT164 v.5 ...

  • Page 18

    ... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

  • Page 19

    ... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15. Contact information For more information, please visit: For sales office addresses, please send an email to: 74HC_HCT164 Product data sheet 14 ...

  • Page 20

    ... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13 Revision history ...