CXA3572 Sony Corporation, CXA3572 Datasheet - Page 28

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CXA3572

Manufacturer Part Number
CXA3572
Description
Driver/Timing Generator for Color LCD Panels
Manufacturer
Sony Corporation
Datasheet

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Description of Serial Control Operation
1) System reset
After turning on the power, activate the TG block system reset by setting XCLR (Pin 35) Low. (See Fig. )
The serial bus is set to the default values.
2) Control method
Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCK. This loading
operation starts from the falling edge of SEN and is completed at the next rising edge.
Digital block control data is established by the vertical sync signal, so if data is transferred multiple times for
the same item, the data immediately before the vertical sync signal is valid. Analog (electronic attenuator)
block control data becomes valid each time the SEN signal is input.
In addition, if 16 bits or more of SCK are not input while SEN is low, the transferred data is not loaded to the
inside of the IC and is ignored. If 16 bits or more of SCK are input, the 16 bits of data before the rising edge of
the SEN pulse are valid data.
SDAT
SCK
SEN
XCLR (Pin 35)
V
DD
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Serial transfer timing
System reset
– 28 –
T
R
T
R
> 10µs
A: ADDRESS
D: DATA
CXA3572R

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