AK4185 AKM [Asahi Kasei Microsystems], AK4185 Datasheet - Page 19

• Manufacturer Part Number: AK4185
• Manufacturer: AKM [Asahi Kasei Microsystems]

(2) Continuous Mode (CONTINUE bit = “1”)
The timing of sampling and A/D conversion is shown in
Hi-Z state at the falling edge of CSN. The AK4185 latches the 8bit control word serially via the DIN pin at the rising edge
of SCLK. Tracking time is the period from the falling edge of the 5th SCLK to the falling edge of the 8th SCLK. The SAR
A/D conversion is synchronized with SCLK from the falling edge of the 9th SCLK.
If DDLY bit = “0”, the AK4185 outputs 12bit A/D data with MSB first from the falling edge of the 12th SCLK. In this
mode, the AK4185 continuously outputs A/D data according to the number of times by COUNT bit (6 or 10 times A/D
conversion) from the falling edge of the 8th SCLK per 16SCLK cycles. (12bit MSB first, LSB justified)
If DDLY bit = “1”, the AK4185 outputs MSB first 12bit A/D data from the falling edge of the 9th SCLK. In this mode, the
AK4185 continuously outputs A/D data according to the number of times by COUNT bit (6 or 10 times A/D conversion)
from the falling edge of the 9th SCLK per 16SCLK cycles. (12bit MSB first, MSB justified) The A/D data output timing
is the same as Single Mode.
If PD0 bit sets to “1” in continuous mode, A/D converter is powered up between A/D conversions. It helps A/D data
variation to decrease.
In continuous mode, when the AK4185 is executing the operation, the AK4185 ignores all control commands. The
AK4185 can receive the next control command from the rising edge of the 96th SCLK (COUNT bit = “0”) or the 160th
SCLK (COUNT bit = “1”). When the next control command is sent at the rising edge of the 97th SCLK (COUNT bit =
“0”) or the 161st SCLK (COUNT bit = “1”), the AK4185 can output one A/D data per 16 SCLK clock cycles as well as
the continuous mode.
MS0954-E-00
Touch Screen Driver SW (Internal Node)
(DFR Mode, PD0 =”0”)
Touch Screen Driver SW (Internal Node)
(DFR Mode, PD0 =”0”)
SCLK
DOUT
SCLK
DOUT
CSN
CSN
DIN
DIN
Hi-Z
Hi-Z
S
S
1
1
A2
A2
2
2
A1
A1
3
3
Figure 17. External Clock Mode Control Sequence (Continuous Mode: DDLY bit = “0”)
Figure 18.
A0
A0
4
4
MO
MO
5
5
X1
X1
6
6
X2
X2
7
7
PD0
PD0
8
8
External Clock Mode Control Sequence (Continuous Mode: DDLY bit = “1”)
9
9
11
10
10
10
11
11
9
12
12
11
8
13
13
10
7
14
14
Data 1
9
6
15
15
16SCLK
16SCLK
8
5
16
16
4
7
17
17
Data 1
3
6
18
18
5
2
19
19
4
1
20
20
3
0
21
21
2
22
22
1
23
23
Figure 17
- 19 -
0
24
24
25
25
11
26
26
10
27
27
Data 2
16SCLK
16SCLK
9
28
28
and
11
8
29
29
Figure
3
Data 2
0
37
37
2
38
38
1
39
39
0
40
40
18. The DOUT pin changes to “L” from
41
41
42
42
11
11
10
10
9
9
8
8
7
7
Data n
Data n
6
6
5
5
4
4
3
3
2
2
1
1
[AK4185]
0
0
2008/05