ZL50015GAC ZARLINK [Zarlink Semiconductor Inc], ZL50015GAC Datasheet - Page 17

• Manufacturer Part Number: ZL50015GAC
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

B7, C7, B5,
PBGA Pin
J6, D6, H5
H14, D11
Number
F15
B10
LQFP Pin
170, 172,
174, 227,
176, 221
Number
100, 104
108
155
FPo_OFF0 - 1
FPo_OFF2
Pin Name
CKo0 - 5
FPo5
FPi
or
Zarlink Semiconductor Inc.
Generated Offset Frame Pulse Outputs 0 to 1 (5 V-Tolerant
Three-state Outputs)
Individually programmable 8 kHz frame pulses, offset from the
output frame boundary by a programmable number of channels.
Generated Offset Frame Pulse Output 2 or 19.44 MHz Frame
Pulse Output (5 V-Tolerant Three-state Output)
As FPo_OFF2, this is an individually programmable 8 kHz frame
pulse, offset from the output frame boundary by a programmable
number of channels.
By programming the FP19EN (bit 10) of FPOFF2 register to high,
this signal becomes FPo5, a non-offset frame pulse corresponding
to the 19.44 MHz clock presented on CKo5. FPo5 is only available
in Master mode or when the SLV_DPLLEN bit in the Control
Register is set high while the device is in one of the slave modes.
ST-BUS/GCI-Bus Clock Outputs 0 to 5 (5 V-Tolerant
Three-state Outputs)
CKo0: 4.096 MHz output clock.
CKo1: 8.192 MHz output clock.
CKo2: 16.384 MHz output clock.
CKo3: 4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz
programmable output clock.
CKo4: 1.544 MHz or 2.048 MHz programmable output clock.
CKo5: 19.44 MHz output clock.
See Section 6.0 on page 24 for details. In Divided Slave mode, the
frequency of CKo0 - 3 cannot be higher than input clock (CKi).
CKo4 and CKo5 are only available in Master mode or when the
SLV_DPLLEN bit in the Control Register is set high while the
device is in one of the slave modes.
ST-BUS/GCI-Bus
Schmitt-Triggered Input)
This pin accepts the frame pulse which stays active for 61 ns,
122 ns or 244 ns at the frame boundary. The frame pulse
frequency is 8 kHz. The frame pulse associated with the highest
input or output data rate must be applied to this pin when the
device is operating in Divided Slave mode or Master mode. The
exception is if the device is operating in Master mode with
loopback (i.e., CKi_LP is set in the Control Register). In that case,
this input must be tied high or low externally. When the device is
operating in Multiplied Slave mode, the frame pulse associated
with the highest input data rate must be applied to this pin. For all
modes (except Master mode with loopback), if the data rate is
16.384 Mbps, a 61 ns wide frame pulse must be used. By default,
the device accepts a negative frame pulse in ST-BUS format, but it
can accept a positive frame pulse instead if the FPINP bit is set
high in the Control Register (CR). It can accept a GCI-formatted
frame pulse by programming the FPINPOS bit in the Control
Register (CR) to high.
ZL50015
17
Frame
Description
Pulse
Input
(5 V-Tolerant
Data Sheet