ZL50015GAC ZARLINK [Zarlink Semiconductor Inc], ZL50015GAC Datasheet - Page 37

• Manufacturer Part Number: ZL50015GAC
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

and FPi. Therefore, in Divided Slave mode, the output clock rates cannot exceed the CKi rate (the output data rates
are also limited as per Table 1, but in Multiplied Slave mode, all specified output clock rates and data rates are
available on CKo0-3 and STio0-15. The input data rate cannot exceed the CKi rate in either Slave modes, because
input data are always sampled directly by CKi.
By default, CKo4, CKo5 and FPo5 are not available in Slave mode, as the embedded DPLL is disabled. However,
the DPLL can be activated even in Slave mode by programming the SLV DPLLEN bit in the Control Register. When
the DPLL is enabled in Slave mode, CKo4, CKo5 and FPo5 are generated from the DPLL synchronized to one of
the REF0-3 inputs, while the other clocks, frame pulses, and input/output data are synchronized to CKi/FPi. It
basically creates two separate timing domains - one for the DPLL, and one for data switch logic. The two can be
totally asynchronous to each other. In this case the DPLL will be fully functional, including its capability of reference
monitoring.
Note that an external oscillator is required whenever the DPLL is used.
Table 7, “ZL50015 Operating Modes” on page 37 summarizes the different modes of operation available within the
ZL50015. Each Major mode has various associated Minor modes that are determined by setting the relevant Input
Control pins and Control Register bits (Table 17, “Control Register (CR) Bits” on page 53) indicated in the table.
11.1
When the device is in Master mode, the DPLL is phase-locked to the one of four DPLL reference signals, REF0 to
REF3, which are sourced by an external 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or
19.44 MHz signal. The on-chip DPLL also offers reference switching and monitoring, jitter attenuation, freerun and
holdover functions. In this mode, STio0 - 15 are driven by a clock generated by the DPLL, which also provides all
the output clocks (CKo0 - 5) and frame pulses (FPo0 - 3 and FPo_OFF0 - 2). One of the output clocks and frame
pulses should be looped back to CKi/FPi as reference for the input data, either by internal loopback (by setting the
CKi_LP bit high in the Control Register) or through some external loopback paths. If external loopback is used, it is
recommended that CKo2 (16.384MHz) and FPo2 (61ns pulse) are used so that all input data rates are available.
Legend:
X - Don’t care or not applicable.
Reference Lock - Refers to what signal the output pins are locked to:
REF0-3 = Normal Mode
Cki = Bypass. Cki is passed directly through to CKo0-3.
Cki MULT = Cki is passed through clock multiplier to CKo0-3.
* CKi must be phase aligned (edge synchronous) to CKo0-3.
Clock Source - Refers to which clock samples STi and which clock outputs STo; STi applies when STi or STio is input; STo applies when STio is output.
Multiplied
Divided
Master
Major
Slave
Slave
Operating Mode
Device
Master Mode Operation
Loopback
8/16 M
8/16 M
8/16 M
8/16 M
Minor
CKi
4 M
4 M
4 M
4 M
OSC_EN MODE_4M
1
1
0
1
0
Control
[1:0]
00
00
00
00
00
Input Pins
11
11
11
11
20 MHz 4/8/16 M
20 MHz
20 MHz
OSCi
X
X
Signal
Table 7 - ZL50015 Operating Modes
8/16 M
8/16 M
8/16 M
8/16 M
CKi
4 M
4 M
4 M
4 M
X
Zarlink Semiconductor Inc.
OPM
[1:0]
01
X0
X1
11
00
ZL50015
SLV_DPLLEN
CR Register
37
X
1
0
1
0
Bits
CKi_LP
X
0
1
CKi MULT REF0-3
Freerun, Holdover
CKo0-3
Reference Lock
CKi
or REF0-3
Output Clock Pins
REF0-3
CKo4-5 CKo0-3 CKo4-5
X
X
Yes
Enabled
Yes
Yes
Yes
No
No
Data Sheet
Cko2
CKi*
STi
CKi
Clock Source
Data Pins
(CKi MULT)
CKo0-3
CKo0-3
(DPLL)
Cko2
(CKi)
STo