ZL50015GAC ZARLINK [Zarlink Semiconductor Inc], ZL50015GAC Datasheet - Page 35

• Manufacturer Part Number: ZL50015GAC
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

9.0
The connection memory consists of two blocks, Connection Memory Low (CM_L) and Connection Memory High
(CM_H). The CM_L is 16 bits wide and is used for channel switching and other special modes. The CM_H is 5 bits
wide and is used for the voice coding function. When UAEN (bit 15) of the Connection Memory Low (CM_L) is low,
µ-law/A-law conversion will be turned off and the contents of CM_H will be ignored. Each connection memory
location of the CM_L or CM_H can be read or written via the 16 bit microprocessor port within one microprocessor
access cycle. See Table 50 on page 86 for the address mapping of the connection memory. Any unused bits will be
reset to zero on the 16-bit data bus.
For the normal channel switching operation, CMM (bit 0) of the Connection Memory Low (CM_L) is programmed
low. SCA7 - 0 (bits 8 - 1) indicate the source (input) channel address and SSA4 - 0 (bits 13 - 9) indicate the source
(input) stream address. The 5-bit contents of the CM_H will be ignored during the normal channel switching mode
without the µ-law/A-law conversion when UAEN (bit 15) of the Connection Memory Low (CM_L) is set to zero. If
µ-law/A-law conversion is required, the CM_H bits must be programmed first to provide the voice/data information,
the input coding law and the output coding law before the assertion of UAEN (bit 15) in the Connection Memory
Low.
When CMM (bit 0) of the Connection Memory Low (CM_L) is programmed high, the ZL50015 will operate in one of
the special modes described in Table 52 on page 88. When the per-channel message mode is enabled, MSG7 - 0
(bit 10 - 3) in the Connection Memory Low (CM_L) will be output via the serial data stream as message output data.
When the per-channel message mode is enabled, the µ-law/A-law conversion can also be enabled as required.
STio
STio
STi
STi
L = last channel = 31, 63, 127, or 255 for 2.048 Mbps, 4.096 Mbps
L-2
L-2
L-2
L-2
Connection Memory Description
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
Figure 20 - Data Throughput Delay for Constant Delay
Frame N
L-2
L-2
L-2
L-2
Zarlink Semiconductor Inc.
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
ZL50015
35
,
8.192 Mbps, or 16.384 Mbps respectively
Frame N + 1
L-2
L-2
L-2
L-2
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
Data Sheet
Frame N + 2