ZL50015GAC ZARLINK [Zarlink Semiconductor Inc], ZL50015GAC Datasheet - Page 67

• Manufacturer Part Number: ZL50015GAC
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note 1:
External Read Only Address: 0045
14 - 0
Bit
15
15
0
Output frequency offset, relative to master clock, will be represented as the following:
+10 ppm: CFN x 0.00001 = 440 = 01B8
-10 ppm: CFN x (-0.00001) = -440 = 7E48
FOF
14
14
FOF14 - 0
Unused
Name
FOF
13
13
Table 30 - Frequency Offset Register (FOR) Bits - Read Only
FOF
Reserved. In normal functional mode, this bit is zero.
Frequency Offset Bits: The binary value of these bits represents the current deviation
of the DPLL output from its center frequency. Defined in same units as CFN in the 2's
complement format.
12
12
H
FOF
11
11
FOF
10
10
H
FOF
H
9
9
Zarlink Semiconductor Inc.
ZL50015
FOF
8
8
67
FOF
7
7
Description
FOF
6
6
FOF
5
5
FOF
4
4
FOF
3
3
FOF
2
2
Data Sheet
FOF
1
1
FOF
0
0