MD82C284-12/883 INTERSIL [Intersil Corporation], MD82C284-12/883 Datasheet - Page 6

• Manufacturer Part Number: MD82C284-12/883
• Description: Clock Generator and Ready Interface for 80C286 Processors
• Manufacturer: INTERSIL [Intersil Corporation]

Timing Waveforms
NOTE: The EFI input LOW and HIGH times as shown are required to guarantee the CLK LOW and HIGH times shown.
NOTE: This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.
NOTES:
1. This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.
2. If SRDY + SRDYEN or ARDY + ARDYEN are active before and/or during the first bus cycle after RESET, READY may not be deasserted
FIGURE 3. RESET AND READY TIMING AS A FUNCTION OF RES WITH S1, S0, ARDY + ARDYEN AND SRDY + SRDYEN HIGH
until the falling edge of φ2 of T
ARDY + ARDYEN
SRDY + SRDYEN
S1 • S0
READY
PCLK
CLK
READY
RESET
S
.
CLK
RES
FIGURE 4. READY AND PCLK TIMING WITH RES HIGH
t
DEPENDS ON
6
CLK
EFI
t
13
STATE OF
FIGURE 2. CLK AS A FUNCTION OF EFI
t
14
UNDEFINED
φ1
FIRST BUS
t
5A
t
19
PREVIOUS
RES
T
t
S
24
t
(SEE
NOTE)
21
t
82C284/883
t
11
1
CYCLE
IF THIS IS
t
φ2
15A
t
6
t
13
NOTE 2
t
6
16
t
17
t
t
φ1
15B
t
22
t
23
2
NOTE 1
t
5B
t
12
t
9
t
21
t
14
T
t
C
16
t
20
t
11
t
24
φ2
t
t
23
10
t
18
t
25
t
21
t
22
t
12
t
26