ZL50405GDC ZARLINK [Zarlink Semiconductor Inc], ZL50405GDC Datasheet - Page 104

• Manufacturer Part Number: ZL50405GDC
• Description: Managed5-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.3.8.5
CPU Address 711
Accessed by CPU (R/W)
12.3.9
12.3.9.1
I²C Address h04C+n; CPU Address:h800+n (n = port number)
Accessed by CPU and I²C (R/W)
(Group 8 Address) Per Port QOS Control
Bit [3]:
Bits [6:4]:
Bit [7]:
Bits [2:0]:
Bit [3]:
Bits [6:4]:
Bit [7]:
Bits [3:0]:
Bits [6:4]:
Bit [7]:
RMAC_MIRROR1 – RMAC Mirror 1
FCRn – Port 0~3,8,9 Flooding Control Register
Source port to be mirrored
Mirror path
0: Receive
1: Transmit
Destination port for mirrored traffic
Mirror enable
Mirror path
0: Receive
1: Transmit
Destination port for mirrored traffic
Mirror enable
U2MR: Unicast to Multicast Rate. Units in terms of time base defined in bits
[6:4]. This is used to limit the amount of flooding traffic from Port n. The value
in U2MR specifies how many packets are allowed to flood within the time
specified by bit [6:4]. To disable this function, program U2MR to 0.
(Default = 0)
Time Base for Unicast to Multicast, Multicast and Broadcast rate control of
Port n: (Default = 000)
000 = 100 us
001 = 200 us
010 = 400 us
011 = 800 us
100 = 1.6 ms
101 = 3.2 ms
110 = 6.4 ms
111 = 12.8 ms
Reserved
Zarlink Semiconductor Inc.
ZL50405
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Data Sheet