ZL50405GDC ZARLINK [Zarlink Semiconductor Inc], ZL50405GDC Datasheet - Page 68

• Manufacturer Part Number: ZL50405GDC
• Description: Managed5-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.2.7
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12.2.8
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12.3
12.3.1
12.3.1.1
I²C Address 000+n; CPU Address:0000+2n (n = port number)
Accessed by CPU and I²C (R/W)
Port 0 – 3& 9: (RMAC & MMAC Ports)
CPU transmit/receive control frames (8/16 bits)
Address = 6 (read/write)
When CPU writes to this register:
When CPU reads this register:
CPU receive control frames (8/16 bits)
Address = 7 (read only)
When CPU reads this register:
Indirectly Accessed Registers
Control Command Frame Buffer1 Access Register
Control Command Frame Buffer2 Access Register
(Group 0 Address) MAC Ports Group
Bit [0]
Bit [1]
Bit [2]
Bits [4:3]
Data is written to the Control Command Frame Receive Buffer
Data is read from the Control Command Frame Transmit Buffer1
Data is read from the Control Command Frame Transmit Buffer2
ECR1Pn: Port n Control Register
Flow Control
0 - Enable (Default)
1 - Disable
Duplex Mode
0 - Full Duplex (Default)
1 - Half Duplex - Only in 10/100 mode
Speed
0 - 100 Mbps (Default)
1 - 10 Mbps
00 - Enable Auto-Negotiation (Default)
01 - Limited Disable Auto-Negotiation
10 - Force Link Down
11 - Force Link Up
This enables hardware state machine for auto-negotiation.
This disables hardware state machine for speed auto-negotiation (use
Disable the port. Hardware does not talk to PHY.
The configuration in ECR1Pn[2:0] is used for (speed/duplex/flow control)
setup. Hardware does not talk to PHY.
ECR1Pn[2:0] for configuration). Hardware will still poll PHY for link status.
Zarlink Semiconductor Inc.
ZL50405
68
Data Sheet