ZL50405GDC ZARLINK [Zarlink Semiconductor Inc], ZL50405GDC Datasheet - Page 84

• Manufacturer Part Number: ZL50405GDC
• Description: Managed5-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.3.4.14
CPU Address:h329
Accessed by CPU (RW)
12.3.4.15
CPU Address:h330-336
Accessed by CPU, (R/W)
CPU Queue insertion command
12.3.4.16
CPU Address:h337
Accessed by CPU, (RO)
CPU command queue status
Bit[3:0]:
Bit[7:4]:
Bit[9:8]:
Bits [13:10]
Bits [20:14]
Bits [35:21]
Bits [50:36]
Bit [51]
Bits [54:52]
Bit [55]
Bits [7:0]:
Bit [0]:
Bit [1]:
MAC9 – Increment MAC port 9 address
CPUQINS0 - CPUQINS6 – CPU Queue Insertion Command
CPUQINSRPT – CPU Queue Insertion Report
55
CQ6
The command is under processing.
Insertion Fail (May be due to queue full, WRED or filtering)
Bits [47:40] of Port 9 CPU MAC address
Destination Map (port 3-0).
Reserved. Must be 0.
Destination Map (MMAC, CPU).
Priority
Number of granules for the frame
Tail pointer
Header Pointer
Multicast frame (has to be one if more than one destination port)
Reserved
Command valid (will be processed on the rising edge of the signal)
CQ5
CQ4
Zarlink Semiconductor Inc.
ZL50405
CQ3
84
CQ2
CQ1
CQ0
0
Data Sheet