ZL50405GDC ZARLINK [Zarlink Semiconductor Inc], ZL50405GDC Datasheet - Page 117

• Manufacturer Part Number: ZL50405GDC
• Description: Managed5-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.3.11.4
CPU Address:hF03
Accessed by CPU (R/W)
12.3.11.5
CPU Address: hF04
Accessed by CPU (RO)
This register provides various internal information as selected in DPST bit [4:0]. Refer to the PHY Port Control
Application Note, ZLAN-37.
Bits [4:0]:
Bits [7:5]:
Bit [0]
Bit [1]
Bit [2]
Bit [3]
Bit [4]
Bit [5]
Bit [6]
Bit [7]
DPST – Device Port Status Register
DTST – Data read back register
Read back index register. This is used for selecting what to read back from
DTST. (Default 00)
Reserved
Flow control enable
1: Flow control
0: No flow control
Full duplex port
1: Full duplex
0: Half duplex
Fast Ethernet port
1: FE Port
Link is down
1: Link down
0: Link up
Auto negotiation disabled
1: Disable
0: Enable
Reserved
Reserved
Module detected (for hot swap purpose)
0: No module
1: Module detected
Note: If Module Detect feature is disabled (bootstrap TSTOUT[9]=’0’), this bit
will always be ‘1’.
-
-
-
-
-
-
-
5’b00000 - Port 0 Operating mode and Negotiation status
5’b00001 - Port 1 Operating mode and Negotiation status
5’b00010 - Port 2 Operating mode and Negotiation status
5’b00011 - Port 3 Operating mode and Negotiation status
5’b001xx - Reserved
5’b01000 - Port CPU Operating mode and Negotiation status
5’b01001 - Port MMAC Operating mode and Negotiation status
Zarlink Semiconductor Inc.
ZL50405
117
Data Sheet