ZL50405GDC ZARLINK [Zarlink Semiconductor Inc], ZL50405GDC Datasheet - Page 81

• Manufacturer Part Number: ZL50405GDC
• Description: Managed5-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.3.4.2
CPU Address:h301
Accessed by CPU (R/W)
12.3.4.3
CPU Address:h302
Accessed by CPU (R/W)
12.3.4.4
CPU Address:h303
Accessed by CPU (R/W)
12.3.4.5
CPU Address:h304
Accessed by CPU (R/W)
12.3.4.6
CPU Address:h305
Accessed by CPU (R/W)
12.3.4.7
CPU Address:h306
Accessed by CPU (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted. (Default 0x00)
-
-
1: Mask the interrupt
0: Unmask the interrupt (Enable interrupt) (Default)
Bits [7:0]:
Bits [7:0]:
Bits [7:0]:
Bits [7:0]:
Bits [7:0]:
MAC1 – CPU MAC address byte 1
MAC2 – CPU MAC address byte 2
MAC3 – CPU MAC address byte 3
MAC4 – CPU MAC address byte 4
MAC5 – CPU MAC address byte 5
INT_MASK0 – Interrupt Mask
Byte 2 (bits [23:16]) of the CPU MAC address (Default 0)
Byte 1 (bits [15:8]) of the CPU MAC address (Default 0)
Byte 4 (bits [39:32]) of the CPU MAC address (Default 0)
Byte 5 (bits [47:40]) of the CPU MAC address (Default 0)
Note: Bits [42:40] are set on a per port basis using MAC01, MAC23 registers. For
port 9, this register is ignored and MAC9 is used for bits [47:40].
Byte 3 (bits [31:24]) of the CPU MAC address (Default 0)
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Data Sheet