CY7C1049CV33-12ZXI Cypress Semiconductor Corporation., CY7C1049CV33-12ZXI Datasheet
CY7C1049CV33-12ZXI
Manufacturer Part Number
CY7C1049CV33-12ZXI
Description
Manufacturer
Cypress Semiconductor Corporation.
Specifications of CY7C1049CV33-12ZXI
Case
TSOP44
Date_code
2006+
Cypress Semiconductor Corporation
Document #: 38-05063 Rev. **
Features
Functional Description
The CY7C1049 is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. Easy memory expansion
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby
Current (mA)
Shaded areas contain advance information.
• High speed
• Low active power
• Low CMOS standby power (Commercial L version)
• 2.0V Data Retention (400 W at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
CE
WE
OE
Logic Block Diagram
— t
— 1210 mW (max.)
— 2.75 mW (max.)
A
A
A
A
A
A
A
A
A
A
A
10
0
1
2
3
4
5
6
7
8
9
AA
= 15 ns
INPUT BUFFER
DECODER
COLUMN
512K x 8
ARRAY
Com’l
Com’l
Ind’l
Military
POWER
DOWN
•
L
3901 North First Street
PRELIMINARY
7C1049-12
240
0.5
12
8
9
1049–1
is provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. Writing to the de-
vice is accomplished by taking chip enable (CE) and write en-
able (WE) inputs LOW. Data on the eight I/O pins (I/O
I/O
pins (A
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing write en-
able (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on
the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049 is available in a standard 400-mil-wide 36-pin
SOJ package with center power and ground (revolutionary)
pinout.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7C1049-15
7
0
1
2
3
4
5
6
7
) is then written into the location specified on the address
220
0.5
15
8
9
0
•
through A
San Jose
7C1049-17
18
512K x 8 Static RAM
195
).
0.5
17
Pin Configuration
8
9
GND
I/O3
I/O
I/O
V
I/O
•
WE
CE
CC
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
0
1
2
5
6
7
8
9
CA 95134
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
0
SOJ
7C1049-20
through I/O
185
Revised August 31, 2001
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
0.5
20
10
8
9
NC
A
A
A
A
OE
I/O
I/O
GND
V
I/O
I/O
A
A
A
A
A
NC
18
17
16
15
CC
14
13
12
11
10
CY7C1049
7
6
5
4
•
1049–2
7
) are placed in a
408-943-2600
7C1049-25
180
0.5
25
10
0
8
9
through
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