CY7C68013A128AXC Cypress Semiconductor Corporation., CY7C68013A128AXC Datasheet

CY7C68013A128AXC

Manufacturer Part Number

CY7C68013A128AXC

Description

QFP128

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C68013A128AXC.pdf (62 pages)

Specifications of CY7C68013A128AXC

Date_code

08+

Current page: 1 of 62
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Features (CY7C68013A/14A/15A/16A)

■

Cypress Semiconductor Corporation

Document #: 38-08032 Rev. *P

USB 2.0 USB IF High Speed Certified (TID # 40460272)

Single Chip Integrated USB 2.0 Transceiver, Smart SIE, and

Enhanced 8051 Microprocessor

Fit, Form, and Function Compatible with the FX2

❐

Ultra Low Power: I

❐

Software: 8051 Code Runs from:

❐

16 KBytes of On-Chip Code/Data RAM

Four Programmable BULK, INTERRUPT, and

ISOCHRONOUS Endpoints

❐

Additional Programmable (BULK/INTERRUPT) 64 Byte

Endpoint

8-Bit or 16-Bit External Data Interface

Smart Media Standard ECC Generation

Pin compatible

Object code compatible

Functionally compatible (FX2LP is a superset)

Ideal for bus and battery powered applications

Internal RAM, which is downloaded through USB

Internal RAM, which is loaded from EEPROM

External memory device (128 pin package)

Buffering options: double, triple, and quad

No More than 85 mA in any Mode

•198 Champion Court•

EZ-USB FX2LP™ USB Microcontroller

High Speed USB Peripheral Controller

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GPIF (General Programmable Interface)

❐

Integrated, Industry Standard Enhanced 8051

❐

3.3V Operation with 5V Tolerant Inputs

Vectored USB Interrupts and GPIF/FIFO Interrupts

Separate Data Buffers for the Setup and Data Portions of a

CONTROL Transfer

Integrated I

Four Integrated FIFOs

❐

Available in Commercial and Industrial Temperature Grade

(all packages except VFBGA)

Enables direct connection to most parallel interfaces

Programmable waveform descriptors and configuration

registers to define waveforms

Supports multiple Ready (RDY) inputs and Control (CTL)

outputs

48 MHz, 24 MHz, or 12 MHz CPU operation

Four clocks per instruction cycle

Two USARTs

Three counter/timers

Expanded interrupt system

Two data pointers

Integrated glue logic and FIFOs lower system cost

Automatic conversion to and from 16-bit buses

Master or slave operation

Uses external clock or asynchronous strobes

Easy interface to ASIC and DSP ICs

San Jose, CA 95134-1709•

C Controller, Runs at 100 or 400 kHz

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Revised October 12, 2009

408-943-2600

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