SSD1852T2R1 ETC [List of Unclassifed Manufacturers], SSD1852T2R1 Datasheet
SSD1852T2R1
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SSD1852T2R1 Summary of contents
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TABLE OF CONTENTS 1 GENERAL DESCRIPTION ................................................................................................................ 1 2 FEATURES ........................................................................................................................................ 2 3 ORDERING INFORMATION.............................................................................................................. 2 4 BLOCK DIAGRAM............................................................................................................................. 3 5 DIE PAD ARRANGEMENT................................................................................................................ 4 6 PIN DESCRIPTION ............................................................................................................................ 8 RES ............................................................................................................................................ 8 6.1 6.2 PS0 & PS1 .................................................................................................................................. 8 ...
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ROW0~ROW127 ...................................................................................................................... 10 6.20 ICONS....................................................................................................................................... 10 6.21 SEG0~SEG127......................................................................................................................... 10 6.22 OSC1 ........................................................................................................................................ 10 6.23 TEST0~TEST13........................................................................................................................ 10 6.24 TEST_IN0 ................................................................................................................................. 10 6.25 NC ............................................................................................................................................. 10 7 FUNCTIONAL BLOCK DESCRIPTIONS ........................................................................................ 11 7.1 Command Decoder and Command Interface....................................................................... 11 7.2 MPU ...
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LCD Panel Driving Waveform ................................................................................................ 16 8 COMMAND TABLE.......................................................................................................................... 19 9 COMMAND DESCRIPTIONS .......................................................................................................... 25 9.1 Set Lower Column Address ................................................................................................... 25 9.2 Set Upper Column Address ................................................................................................... 25 9.3 Set Internal Regulator Resistor Ratio ................................................................................... 25 9.4 Set ...
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Software Reset ........................................................................................................................ 28 9.26 Exit N-line Inversion ............................................................................................................... 28 9.27 Set Display Data Length......................................................................................................... 28 9.28 Exit Modify-read ...................................................................................................................... 28 9.29 Set TC value............................................................................................................................. 29 9.30 Enable internal oscillator resistor ......................................................................................... 29 9.31 Enable Frame Frequency setting .......................................................................................... ...
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TABLE OF FIGURES Figure 1 - Block Diagram .............................................................................................................................. 3 Figure 2 - Die Pad Assignment ..................................................................................................................... 4 Figure 3 - Display Data Read Back Procedure – Insertion of Dummy Read.............................................. 12 Figure 4 - Oscillator..................................................................................................................................... 12 Figure 5 - ...
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SEMICONDUCTOR TECHNICAL DATA Advance Information LCD Segment / Common Driver With Controller CMOS 1 General Description SSD1852 is a single-chip CMOS LCD driver with controller for liquid crystal dot-matrix graphic display system. It consists of 257 high voltage driving output ...
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... Programmable COM output sequence Direct memory access mode Selectable internal/external oscillator resistor Available in gold bump die and TAB (Tape Automated Bonding) Package 3 ORDERING INFORMATION Table 1 - Ordering Information Ordering Part Number SSD1852Z SSD1852TR1 SSD1852T2R1 SSD1852 Rev 1.0 01/2003 adjustment L6 Seg Com 128 128 + 1 128 ...
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BLOCK DIAGRAM Display Timing Generator Oscillator OSC1 TEST0 : TEST13 TEST_IN0 Command Interface RES PS0 PS1 3 SSD1852 Rev 1.0 01/2003 ROW0 ~ ICONS SEG0 ~ SEG 127 ROW127 HV Buffer Cell Level Shifter Display ...
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DIE PAD ARRANGEMENT SSD1852 Rev 1.0 01/2003 Note: Die Size: 10. 1.72mm Die Thickness: 533±25µm Bump Height: Typical 18µm Bump co-planarity <3µm (within die) Figure 2 - Die Pad Assignment 1. Diagram showing the face of the ...
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Signal Pad # X-pos 1 ROW124 -4763.1 2 ROW125 -4700.1 3 ROW126 -4650.1 4 ROW127 -4600.1 5 ICONS -4550.1 6 TEST8 -4457.9 7 TEST9 -4381.7 8 TEST0 -4305.5 9 TEST1 -4229.3 10 TEST2 -4153.1 11 TEST3 -4076.9 12 TEST4 -4000.7 ...
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Pad # Signal X-pos Y-pos 151 ROW37 5094.1 400.0 152 ROW36 5094.1 450.0 153 ROW35 5094.1 500.0 154 ROW34 5094.1 550.0 155 ROW33 5094.1 600.0 156 ROW32 5094.1 650.0 157 ROW31 5094.1 713.0 158 ROW30 4762.9 705.0 159 ROW29 4699.9 ...
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Pad # Signal X-pos Y-pos 301 SEG111 -2400.1 705.0 302 SEG112 -2450.1 705.0 303 SEG113 -2500.1 705.0 304 SEG114 -2550.1 705.0 305 SEG115 -2600.1 705.0 306 SEG116 -2650.1 705.0 307 SEG117 -2700.1 705.0 308 SEG118 -2750.1 705.0 309 SEG119 -2800.1 ...
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PIN DESCRIPTION 6.1 RES This pin is reset signal input. When the pin is low, initialization of the chip is executed. 6.2 PS0 & PS1 These two pins determine the interface protocol between the driver and MCU. Refer to ...
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REF This pin is an input pin to enable the internal reference voltage used for the internal regulator. When it is high, an internal reference voltage source will be used. When it is low, an external reference voltage source ...
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ROW0~ROW127 These pins provide the row driving signals ROW0 – ROW127 to the LCD panel. 6.20 ICONS This pin is the special icon line ROW signal output. 6.21 SEG0~SEG127 These pins provide the LCD column driving signals. Their voltage ...
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FUNCTIONAL BLOCK DESCRIPTIONS 7.1 Command Decoder and Command Interface This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the Graphic Display Data RAM (GDDRAM). ...
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Modes of operation 6800 parallel Data Read Data Write Command Read Status only Command Write write column address Figure 3 - Display Data Read Back Procedure – Insertion of ...
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LCD Driving voltage Generator and Regulator This module generates the LCD voltage needed for display output. It takes a single supply input and generates necessary bias voltages. It consists of: 7.8.1 3X, 4X, 5X and 6X DC-DC voltage converter ...
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Figure 6 - Voltage Regulator Output for Different Gain/Contrast Settings (V DC-DC level = 6X; TC2 = -0.125%/ 7.8.4 Bias Divider If the output op-amp buffer option in Set ...
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Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 128 x 129 33024 bits. Figure description ...
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Display Data Latch This block is a series of latches carrying the display signal information. These latches hold the data, which will be fed to HV Buffer Cell and Level Selector to output the required voltage levels. The number ...
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First Byte (LSB) Page Address Page ...
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COM0 COM1 SEG0 SEG1 * Note : N is the number of multiplex ratio including Icon line enabled equal to 128 on POR. ...
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COMMAND TABLE Table 3 - Command Table ( D/ C Bit Pattern 0000 0001 0010 0010 1VC VR VF ...
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Bit Pattern 0100 11XX XXXN 0101 0110 01B 1000 0001 XXC ...
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Bit Pattern 1010 000S 0 1010 001C 0 1010 010E 0 1010 011R 0 1010 100P 1010 1011 1010 111D 0 1011 1100 S XXX 0 1110 0000 1110 0001 1110 0010 ...
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Table 4 – Extended Command Table Bit Pattern 1111 0001 0000 1111 1000 X 111 0000 0 1111 1011 0000 X 000 0 1111 1100 0000 1 0 1000 0010 0 ...
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Bit Pattern 1000 0011 1111 0100 0000 1000 0100 0000 ...
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Address Increment Table (Automatic) Comment Write Command 0 1 Read Status 1 0 Write Data 1 1 Read Data Address Increment is done automatically after data read/write. The column address pointer ...
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COMMAND DESCRIPTIONS 9.1 Set Lower Column Address This command specifies the lower nibble of the 7-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the ...
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Set DC-DC Converter Factor Internal DC-DC converter factor is set by this command multiplying factors could be selected. 9.11 Set Contrast Control Register This command adjusts the contrast of the LCD panel by changing V voltage ...
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Set PWM and FRC This command is used to select the number of frames used in frame rate control, and the number of levels in the pulse width modulation. 9.14 Set Segment Re-map This command changes the mapping between ...
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Exit Power-save Mode This command releases the chip from either Standby or Sleep Mode and return to normal operation. 9.25 Software Reset When the RESET instruction is issued, the following parameters are initialized: Register Page address Column address Display ...
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EXTENDED COMMANDS These commands are used, in addition to basic commands, to trigger the enhanced features, on top of general ones, designed for the chip. 9.29 Set TC value This command is to set 1 out of 8 different temperature ...
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OTP setting and programming OTP (One Time Programming method to adjust V variations of LCD module in term of contrast level, OTP can be used to achieve the best contrast of every LCD modules. OTP setting and ...
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Step 2. OTP programming (6) Hardware Reset (sending an active low reset pulse to (7) Enable Oscillator (0xAB) and Exit Sleep Mode (0xE1) (8) Connect an external V (9) Send OTP setting commands that we find in step 1 (0x82, ...
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Start Step 1 i) Hardware reset ii) Send original initialization routines iii) Set and display any test patterns Adjust the contrast level to the best visual level Accept the contrast level on panel? Yes OTP setting steps = Adjusted contrast ...
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OTP Example program Find the OTP offset: 1. Hardware reset by sending an active low reset pulse to 2. COMMAND(0XAB); \\Enable oscillator; COMMAND(0X2F); \\ turn on the internal voltage booster, internal regulator and output op-amp buffer; Select booster level. 3. ...
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Enable DMA mode This command enables the DMA mode. The column address will be incremented by each data access returning to pre-set start column address once overflow (> end column address). The page address will be incremented by column ...
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Lock/Unlock Interface After sending the lock command, the interface will be disabled until the unlock command is received. The lock command is suggested whenever the LCD driver will not be accessed for some period. This can minimize incorrect data ...
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MAXIMUM RATINGS Table 5 - Maximum Ratings (Voltage Reference to V Symbol Parameter V DD Supply voltage Booster Supply Voltage CI V Input Voltage in Current Drain Per Pin Excluding V I and ...
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Symbol Parameter V External Reference Voltage Input REF Internal Reference Voltage V Output High voltage (D -D OH1 0 V Output Low Voltage (D -D OL1 0 V LCD Driving Voltage Source (V L6 Pin) V LCD Driving Voltage Source ...
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Symbol Parameter Temperature Coefficient Compensation PTC0 Flat Temperature Coefficient Temperature Coefficient 1* PTC1 Temperature Coefficient 2* [POR] PTC2 Temperature Coefficient 3* PTC3 Temperature Coefficient 4* PTC4 Temperature Coefficient 5* PTC5 PTC6 Temperature Coefficient 6* Temperature Coefficient 7* PTC7 *The formula ...
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AC CHARACTERISTICS Table Characteristics (Unless otherwise specified, Voltage Referenced Symbol Parameter F Oscillation Frequency of Display OSC Timing Generator F Frame Frequency FRM 39 SSD1852 Rev 1.0 01/2003 Test ...
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The formula for the Frame Frequency is: F OSC F FRM Mux * PWM Remarks: F will be fine tuned automatically, while change Mux ratio. Therefore, the frame frequency OSC always within +/- 10Hz of the target frame frequency. 400 ...
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Table 8 – 6800-Series MPU Parallel Interface Timing Characteristics (V +85 C) Symbol t Clock Cycle Time (write cycle) cycle t Address Setup Time AS t Address Hold Time AH t Write Data Setup Time DSW t Write Data Hold ...
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Table 9 - 8080-Series MPU Parallel Interface Timing Characteristics (V +85 C) Symbol t Clock Cycle Time (write cycle) cycle t Address Setup Time AS t Address Hold Time AH t Write Data Setup Time DSW t Write Data Hold ...
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Table 10 – 3-wires Serial Interface Timing Characteristics (V Symbol tcycle Clock Cycle Time t Chip Select Setup Time CSS t Chip Select Hold Time CSH t Write Data Setup Time DSW t Write Data Hold Time DHW t Clock ...
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Table 11 – 4-wires Serial Interface Timing Characteristics (V Symbol tcycle Clock Cycle Time t Address Setup Time AS t Address Hold Time AH t Chip Select Setup Time CSS t Chip Select Hold Time CSH t Write Data Setup ...
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APPLICATION EXAMPLES ICONS COM0 : : : : COM62 COM63 SEG0 Remapped COM SCAN Direction [Command: C8 SEG127………………………………………………………………………SEG0 : : : : : : RES RES ...
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APPENDIX 14.1 TAB Drawing SSD1852 Rev 1.0 01/2003 Figure 20 – SSD1852T TAB Drawing 1 46 SOLOMON ...
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SSD1852 Rev 1.0 01/2003 Figure 21 – SSD1852T TAB Drawing 2 SOLOMON ...
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SSD1852 Rev 1.0 01/2003 Figure 22 – SSD1852T2 TAB Drawing 1 48 SOLOMON ...
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SSD1852 Rev 1.0 01/2003 Figure 23 – SSD1852T2 TAB Drawing 2 SOLOMON ...
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Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability ...