SSD1852T2R1 ETC [List of Unclassifed Manufacturers], SSD1852T2R1 Datasheet - Page 16

• Manufacturer Part Number: SSD1852T2R1
• Description: LCD Segment / Common Driver With Controller CMOS
• Manufacturer: ETC [List of Unclassifed Manufacturers]

7
11
SSD1852
7.1
7.2
7.3
7.4
7.5
FUNCTIONAL BLOCK DESCRIPTIONS
Command Decoder and Command Interface
is directed to this module based upon the input of the
Graphic Display Data RAM (GDDRAM). If
Command and it will be decoded and written to the corresponding command register.
Reset is of the same function as Power ON Reset (POR). Once
pulse of about 10us, all internal circuitry will be back to its initial status. Refer to Command
Description section for more information.
MPU Parallel 6800-series Interface
E( RD )
RAM (GDDRAM) or the status register.
Display Data RAM or Internal Command Registers depending on the status of
E( RD )
respectively. Refer to Figure 15 of parallel timing characteristics for Parallel Interface Timing
Diagram of 6800-series microprocessors for details.
In order to match the operating frequency of display RAM with that of the microprocessor,
pipeline processing is internally performed which requires the insertion of a dummy read before
the first actual display data read. This is shown in Figure 3.
MPU Parallel 8080-series interface
D/ C
the D
cycle when
Timing Diagram of 8080-series microprocessor.
Similar to 6800-series interface, a dummy read is also required before the first actual display
data read.
MPU Serial 4-wire Interface
shifted into an 8-bit shift register on every rising edge of SCK in the order of D
sampled on every eighth clock cycles and the data byte in the shift register is written to the
Display Data RAM or command register in the same clock cycle. No extra clock cycle or
command is required to end the transmission.
MPU Serial 3-wire Interface
Data Length command is used to indicate a specified number display data byte (1-256) to be
transmitted. Next byte after the display data string is handled as a command.
It should be noted that if there is a signal glitch at SCK that causing an out of synchronization in
the serial communication, a hardware reset pulse at
re-synchronization.
and
0
~D
This module determines whether the input data is interpreted as data or command. Data
The parallel interface consists of 8 bi-directional data pins (D
The parallel interface consists of 8 bi-directional data pins (D
The serial interface consists of serial clock SCK, serial data SDA,
Operation is similar to 4-wire serial interface while
and
and
7
Rev 1.0
01/2003
CS
a display data or status register read.
CS
CS
CS
. The
.
input serves as data latch signal (clock) when they are high and low
is low. Refer to Figure 16 of parallel timing characteristics for Parallel Interface
R/ W ( WR )
CS
input serves as data latch signal (clock) when it is low.
input High indicates a read operation from the Graphic Display Data
R/ W ( WR )
D/ C
is low, the input at D
WR
input Low indicates a write operation to
RES
and
D/ C
D/ C
pin is required to initialize the chip for
RD
pin. If
is not been used. The Set Display
inputs indicate a write or read
RES
D/ C
0
0
0
-D
-D
-D
is high, data is written to
receives a negative reset
7
7
7
),
),
is interpreted as a
D/ C
R/ W ( WR )
R/ W ( WR )
and
7
D/ C
D/ C
, D
6
,... D
CS
determines
,
,
input. The
D/ C
E( RD )
. SDA is
SOLOMON
0
.
,
D/ C
,
is