GS880E32T-100 GSI [GSI Technology], GS880E32T-100 Datasheet

GS880E32T-100

Manufacturer Part Number

GS880E32T-100

Description

512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs

Manufacturer

GSI [GSI Technology]

Datasheet

1.GS880E32T-100.pdf (25 pages)

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipelined

• Dual Cycle Deselect (DCD) operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• 100-lead TQFP package

Functional Description

Applications

The GS880E18/32/36T is a 9,437,184-bit (8,388,608-bit for

x32 version) high performance synchronous SRAM with a 2-

bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV) and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

Rev: 1.11 11/2000

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Through

Pipeline

3-1-1-1

2-1-1-1

operation

Flow

tCycle

225 mA

180 mA

4.0 ns

10 ns

11 ns

15 ns

-11

225 mA

180 mA

11.5 ns

4.0 ns

10 ns

15 ns

-11.5

512K x 18, 256K x 32, 256K x 36

225 mA

180 mA

4.0 ns

10 ns

12 ns

15 ns

-100

8Mb Sync Burst SRAMs

200 mA

175 mA

12.5 ns

4.5 ns

14 ns

15 ns

-80

185 mA

165 mA

5.0 ns

15 ns

18 ns

20 ns

-66

1/25

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through / Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

DCD Pipelined Reads

The GS880E18/32/36T is a DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. SCD (Single Cycle Deselect)

versions are also available. DCD SRAMs pipeline disable

commands to the same degree as read commands. DCD RAMs

hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of

clock.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the byte write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(high) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS880E18/32/36T operates on a 3.3 V power supply, and

all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

from the internal circuit.

GS880E18/32/36T-11/11.5/100/80/66

DDQ

) pins are used to decouple output noise

3.3 V and 2.5 V I/O

100 MHz–66 MHz

Preliminary

3.3 V V

Related parts for GS880E32T-100

GS880E32T-100 Summary of contents

Page 1

... DD Functional Description Applications The GS880E18/32/36T is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2- bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support ...

Page 2

GS880E18 100-Pin TQFP Pinout 100 DDQ ...

Page 3

GS880E32 100-Pin TQFP Pinout 100 DDQ ...

Page 4

GS880E36 100-Pin TQFP Pinout 100 DDQ ...

Page 5

TQFP Pin Description Pin Location 37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 ...

Page 6

GS880E32 Block Diagram Register A0– LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version ...

Page 7

Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Note: There are pull-up devices on the LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be ...

Page 8

Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...

Page 9

Simplified State Diagram Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and ...

Page 10

Simplified State Diagram with G Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make ...

Page 11

Absolute Maximum Ratings (All voltages reference Symbol Description V Voltage Voltage in V DDQ DDQ V Voltage on Clock Input Pin CK V Voltage on I/O Pins I/O V Voltage on Other ...

Page 12

... Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP) Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper- ature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 1 ...

Page 13

AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...

Page 14

Operating Currents Parameter Test Conditions Symbol Device Selected; Operating Pipeline All other inputs Current Output open Flow-Thru Standby Pipeline 0.2V DD Current Flow-Thru Device Deselected; Deselect Pipeline All other inputs Current V ...

Page 15

AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Clock to Output Valid Flow- Thru Clock to Output Invalid Clock to Output in Low-Z Clock ...

Page 16

Write Cycle Timing Single Write ADSP tS tH ADSC tS tH ADV ADV must be inactive for ADSP Write – WR1 –B WR1 ...

Page 17

Flow Through Read-Write Cycle Timing Single Read ADSP ADSC ADV – RD1 – tOE G ...

Page 18

Flow Through Read Cycle Timing Single Read ADSP ADSC ADV –A RD1 – tOLZ ...

Page 19

Pipelined DCD Read Cycle Timing Single Read ADSP ADSC ADV –A RD1 – Hi-Z ...

Page 20

Pipelined DCD Read-Write Cycle Timing Single Read ADSP ADSC tS tH ADV – RD1 – ...

Page 21

... Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention ...

Page 22

Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 0.0 -20.0 -40.0 -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0 Rev: 1.11 11/2000 Specifications cited are subject to change without notice. For ...

Page 23

TQFP Package Drawing Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body 13.9 e ...

Page 24

... GS880E18T-11.5I 514K x 18 GS880E18T-100I 514K x 18 GS880E18T-80I 514K x 18 GS880E18T-66I 256K x 32 GS880E32T-11I 256K x 32 GS880E32T-11.5I 256K x 32 GS880E32T-100I 256K x 32 GS880E32T-80I 256K x 32 GS880E32T-66I 256K x 36 GS880E36T-11I 256K x 36 GS880E36T-11.5I 256K x 36 GS880E36T-100I 256K x 36 GS880E36T-80I 256K x 36 ...

Page 25

Revision History Types of Changes DS/DateRev. Code: Old; Format or Content New GS880E18/32/36TRev1.04h 5/1999; 1.05 9/1999I GS880E18/32/36T1.05 11/ 1999K880E18/32/36T1.06 1/ 2000L GS880E18/32/36T1.06 1/ 2000L; GS880E18/32/36T1.07 3/ 2000N; GS880E18/32/36T1.07 3/ 2000N; GS880E18/32/36T1.08 3/ 2000O; GS880E18/32/36T1.08 3/ 2000O; 880E183236_r1_09 880E18_r1_09; 880E18_r1_10 880E18_r1_10; ...

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