GS8642ZV18B-200I GSI [GSI Technology], GS8642ZV18B-200I Datasheet
GS8642ZV18B-200I
Related parts for GS8642ZV18B-200I
GS8642ZV18B-200I Summary of contents
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... The GS8642ZV18/36/ 72Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. ...
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GS8642ZV72C Pad Out–209-Bump BGA—Top View DQP DQP DDQ ...
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GS8642ZV72 209-Bump BGA Pin Description Symbol Type I ...
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GS8642ZV72 209-Bump BGA Pin Description Symbol Type I TMS I TDI O TDO I TCK DDQ Rev: 1.02 5/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...
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GS8642ZV36B Pad Out–119-Bump BGA—Top View DDQ DQC E DQC F V DDQ G DQC H DQC J V DDQ K DQD L DQD M V DDQ N DQD P DQD R NC ...
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... GS8642ZV18B Pad Out–119-Bump BGA—Top View DDQ DQB DDQ DQB J V DDQ DQB M V DDQ N DQB DDQ Bump BGA— Rev: 1.02 5/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...
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GS8642ZV18/36 119-Bump BGA Pin Description Symbol Type I — ...
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... A B cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock ...
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... Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. ...
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Pipelined and Flow Through Read Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition ...
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Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.02 5/2005 Specifications cited are subject to change without notice. ...
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B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.02 5/2005 Specifications cited are subject to change without notice. For latest documentation see ...
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... SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode ...
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... During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. ...
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Absolute Maximum Ratings (All voltages reference Symbol Voltage in V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O ...
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Logic Levels Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless ...
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AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
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Operating Currents Parameter Test Conditions (x72) Device Selected; All other inputs Operating (x32/ ≥V or ≤ V Current x36 Output open (x18) Standby ZZ ≥ V – 0.2 V — DD Current Device Deselected; Deselect All other inputs ...
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AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid (x18/x36) Clock to Output Valid (x72) Pipeline Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to ...
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Write A Read CKE ADV Rev: 1.02 5/2005 Specifications cited are subject to change without notice. For latest documentation ...
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Write A Write CKE ADV A0– D(A) G *Note High(False ...
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JTAG Pin Descriptions Pin Pin Name I/O Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate TCK Test Clock In from the falling edge of TCK. The TMS input is sampled ...
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TDI TMS TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded ...
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ID Register Contents Die Revision Code Bit # x72 ...
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Test Logic Reset 1 0 Run Test Idle 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to ...
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Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the ...
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JTAG Port Recommended Operating Conditions and DC Characteristics Parameter 1.8 V Test Port Input High Voltage 1.8 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage ...
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... TCK TDI TMS TDO Parallel SRAM input JTAG Port AC Electrical Characteristics Parameter Symbol TCK Cycle Time tTKC TCK Low to TDO Valid tTKQ TCK High Pulse Width tTKH TCK Low Pulse Width tTKL TDI & TMS Set Up Time tTS TDI & TMS Hold Time ...
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BGA Package Drawing (Package Body, 1.0 mm Bump Pitch Bump Array A aaa e Symbol Min Typ A A1 0.40 0.50 ∅b 0.50 0.60 c 0.31 0.36 D 21.9 22.0 ...
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... GS8642ZV36B-300 GS8642ZV36B-250 GS8642ZV36B-200 GS8642ZV36B-167 GS8642ZV72C-300 GS8642ZV72C-250 GS8642ZV72C-200 GS8642ZV72C-167 GS8642ZV18B-300I GS8642ZV18B-250I GS8642ZV18B-200I GS8642ZV18B-167I GS8642ZV36B-300I GS8642ZV36B-250I GS8642ZV36B-200I GS8642ZV36B-167I GS8642ZV72C-300I GS8642ZV72C-250I GS8642ZV72C-200I GS8642ZV72C-167I Notes: 1. ...
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... GS8642ZV72GC-167I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8642ZV18B-167IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... Sync SRAM Datasheet Revision History Types of Changes DS/DateRev. Code: Old; Format or Content New 8642ZVxx_r1 8642ZVxx_r1; 8642ZVxx_r1_01 8642ZVxx_r1_01; 8642ZVxx_r1_02 Rev: 1.02 5/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8642ZV18(B)/GS8642ZV36(B)/GS8642ZV72(C) Page;Revisions;Reason • Creation of new datasheet • ...