GS8642ZV18B-200I GSI [GSI Technology], GS8642ZV18B-200I Datasheet - Page 24

• Manufacturer Part Number: GS8642ZV18B-200I
• Description: 72Mb Pipelined and Flow Through Synchronous NBT SRAM
• Manufacturer: GSI [GSI Technology]

ID Register Contents
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.02 5/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Bit #
x72
x36
x32
x18
x16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
X
X
X
X
X
Revision
X
X
X
X
X
Code
Die
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Not Used
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
24/32
0
0
0
0
0
0
0
0
0
0
GS8642ZV18(B)/GS8642ZV36(B)/GS8642ZV72(C)
0
0
0
0
0
0
0
0
0
0
Configuration
1
1
1
1
1
0
0
1
0
1
I/O
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0 0 1 1 0 1 1 0 0 1
0 0 1 1 0 1 1 0 0 1
0 0 1 1 0 1 1 0 0 1
0 0 1 1 0 1 1 0 0 1
0 0 1 1 0 1 1 0 0 1
GSI Technology
JEDEC Vendor
ID Code
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© 2004, GSI Technology
0
1
1
1
1
1