GS820E32AGT-133 GSI [GSI Technology], GS820E32AGT-133 Datasheet

GS820E32AGT-133

Manufacturer Part Number

GS820E32AGT-133

Description

64K x 32 2Mb Synchronous Burst SRAM

Manufacturer

GSI [GSI Technology]

Datasheet

1.GS820E32AGT-133.pdf (21 pages)

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TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipelined opera-

• Dual Cycle Deselect (DCD) operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP package

• Pb-Free 100-lead TQFP package available

Functional Description

Applications

The GS820E32A is a 2,097,152-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

Rev: 1.07 10/2004

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

tion

2Mb Synchronous Burst SRAM

, E

), address burst

1/21

64K x 32

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output Register can be controlled by

the user via the FT mode pin (Pin 14 in the TQFP). Holding

the FT mode pin low places the RAM in Flow Through mode,

causing output data to bypass the Data Output Register.

Holding FT high places the RAM in Pipelined mode,

activating the rising-edge-triggered Data Output Register.

DCD Pipelined Reads

The GS820E32A is a DCD (Dual Cycle Deselect) pipelined

synchronous SRAM. SCD (Single Cycle Deselect) versions are

also available. DCD SRAMs pipeline disable commands to the

same degree as read commands. DCD SRAMs hold the

deselect command for one full cycle and then begin turning off

their outputs just after the second rising edge of the clock.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS820E32A operates on a 3.3 V power supply and all

inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

from the internal circuit.

DDQ

) pins are used to decouple output noise

GS820E32AT-180/166/133/4/5

3.3 V and 2.5 V I/O

180 MHz–133 MHz

3.3 V V

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