GS8644V72C-250I GSI [GSI Technology], GS8644V72C-250I Datasheet

GS8644V72C-250I

Manufacturer Part Number

GS8644V72C-250I

Description

4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs

Manufacturer

GSI [GSI Technology]

Datasheet

1.GS8644V72C-250I.pdf (40 pages)

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119-, 165-, & 209-Pin BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 1.8 V +10%/–10% core power supply and I/O

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-, 165-, and 209-bump BGA package

Functional Description

Applications

The GS8644V18/36/72 is a

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Rev: 1.03 11/2004

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

75,497,472 -bit high performance

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

72Mb S/DCD Sync Burst SRAMs

4M x 18, 2M x 36, 1M x 72

Curr (x18)

Curr (x36)

Curr (x72)

Curr (x18)

Curr (x36)

Curr (x72)

tCycle

(x18/x36)

(x72)

Parameter Synopsis

1/40

-250 -225 -200 -166 -150 -133 Unit

385

450

540

265

290

345

2.3

2.6

4.0

6.5

360

415

505

265

290

345

GS8644V18(B/E)/GS8644V36(B/E)/GS8644V72(C)

2.5

2.7

4.4

6.5

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

SCD and DCD Pipelined Reads

The GS8644V18/36/72 is a SCD (Single Cycle Deselect) and

DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

Core and Interface Voltages

The GS8644V18/36/72 operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate output

power (V

internal circuits and are 3.3 V and 2.5 V compatible.

335

385

460

265

290

345

2.7

2.8

5.0

6.5

305

345

405

255

280

335

2.9

6.0

8.0

DDQ

) pins are used to decouple output noise from the

295

325

385

240

265

315

3.3

6.7

8.5

265

295

345

225

245

300

3.5

7.5

8.5

Product Preview

250 MHz–133MHz

1.8 V V

1.8 V I/O

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