GS880V18BGT-200 GSI [GSI Technology], GS880V18BGT-200 Datasheet

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GS880V18BGT-200

Manufacturer Part Number
GS880V18BGT-200
Description
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.02 3/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• FT pin for user-configurable flow through or pipeline
• Single Cycle Deselect (SCD) operation
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS880V18/32/36BT is a 9,437,184-bit (8,388,608-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
operation
Flow Through
Pipeline
3-1-1-1
2-1-1-1
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
Curr (x32/x36)
Curr (x32/x36)
Curr (x18)
Curr (x18)
tCycle
tCycle
t
t
KQ
KQ
Parameter Synopsis
1/23
-333
245
275
195
220
2.5
3.0
4.5
4.5
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS880V18/32/36BT is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS880V18/32/36BT operates on a 1.8 V power supply.
All input are 1.8 V compatible. Separate output power (V
pins are used to decouple output noise from the internal circuits
and are 1.8 V compatible.
-300
225
250
180
200
2.5
3.3
5.0
5.0
-250
195
220
155
175
2.5
4.0
5.5
5.5
GS880V18/32/36BT-333/300/250/200
-200
165
185
140
155
3.0
5.0
6.5
6.5
Unit
mA
mA
mA
mA
ns
ns
ns
ns
© 2004, GSI Technology
333 MHz–200 MHz
1.8 V V
1.8 V I/O
DDQ
DD
)

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GS880V18BGT-200 Summary of contents

Page 1

... Pb-Free 100-lead TQFP package available Functional Description Applications The GS880V18/32/36BT is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support ...

Page 2

DDQ ...

Page 3

DDQ ...

Page 4

DQP DDQ ...

Page 5

TQFP Pin Description Symbol Type I — ...

Page 6

Register – LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version shown ...

Page 7

Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Note: There is a pull-up device onthe FT pin and a pull-down device on the ZZ pin, so thosethis input pins can be unconnected and the ...

Page 8

Byte Write Truth Table Function GW Read H Read H Write byte a H Write byte b H Write byte c H Write byte d H Write all bytes H Write all bytes L Notes: 1. All byte outputs are ...

Page 9

Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...

Page 10

Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B that ADSP is tied ...

Page 11

Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles ...

Page 12

Absolute Maximum Ratings (All voltages reference Symbol DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O Pin OUT P ...

Page 13

Logic Levels Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless ...

Page 14

AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...

Page 15

Operating Currents Parameter Test Conditions (x32/ Device Selected; All other inputs Operating ≥V or ≤ V Current IH IL Output open (x18) Standby ZZ ≥ V – 0 Current Device Deselected; Deselect All other inputs Current ≥ V ...

Page 16

AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock to ...

Page 17

Begin Read A Cont Single Read Single Read CK ADSP tS tH ADSC tS ADV tS tH A0– Ba– tOE DQa–DQd Rev: 1.02 3/2005 Specifications cited ...

Page 18

Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tS tH ADV tS tH A0– Ba– and E3 only sampled with ADSC tOE ...

Page 19

... During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. ...

Page 20

TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...

Page 21

... GS880V36BT-200I 512K x 18 GS880V18BGT-333 512K x 18 GS880V18BGT-300 512K x 18 GS880V18BGT-250 512K x 18 GS880V18BGT-200 256K x 32 GS880V32BGT-333 256K x 32 GS880V32BGT-300 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880V18BT-200IT. 2. ...

Page 22

... GS880V36BGT-300 256K x 36 GS880V36BGT-250 256K x 36 GS880V36BGT-200 512K x 18 GS880V18BGT-333I 512K x 18 GS880V18BGT-300I 512K x 18 GS880V18BGT-250I 512K x 18 GS880V18BGT-200I 256K x 32 GS880V32BGT-333I 256K x 32 GS880V32BGT-300I 256K x 32 GS880V32BGT-250I 256K x 32 GS880V32BGT-200I 256K x 36 GS880V36BGT-333I 256K x 36 GS880V36BGT-300I 256K x 36 ...

Page 23

... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 880VxxB_r1 880VxxB_r1; 880VxxB_r1_01 880VxxB_r1_01; 880VxxB_r1_02 Rev: 1.02 3/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. • Creation of new datasheet • Added Pb-free information for TQFP Content • ...

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