GS880Z18-100 GSI [GSI Technology], GS880Z18-100 Datasheet

GS880Z18-100

Manufacturer Part Number

GS880Z18-100

Description

8Mb Pipelined and Flow Through Synchronous NBT SRAMs

Manufacturer

GSI [GSI Technology]

Datasheet

1.GS880Z18-100.pdf (25 pages)

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• 512K x 18 and 256K x 36 configurations

• User configurable Pipeline and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

• Fully pin compatible with both pipelined and flow through

• Pin compatible with 2M, 4M and 16M (future) devices

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleave Burst mode

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• Clock Control, registered address, data, and control

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

Functional Description

The GS880Z18/36T is an 8Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

Rev: 1.10 8/2000

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Pipeline

3-1-1-1

Flow Through

2-1-1-1

Flow Through

read-write-read bus utilization

NtRAM™, NoBL™ and ZBT™ SRAMs

Read/Write

Pipelined

Address

Data I/O

Clock

Cycle

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

210 mA

150 mA

4.5 ns

10 ns

11 ns

15 ns

-11

8Mb Pipelined and Flow Through

210 mA

150 mA

Synchronous NBT SRAMs

4.5 ns

10 ns

12 ns

15 ns

-100

190 mA

130 mA

12.5 ns

4.8 ns

14 ns

15 ns

-80

170 mA

130 mA

15 ns

18 ns

20 ns

5 ns

-66

1/25

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS880Z18/36T may be configured by the user to operate

in Pipeline or Flow Through mode. Operating as a pipelined

synchronous device, in addition to the rising-edge-triggered

registers that capture input signals, the device incorporates a

rising-edge-triggered output register. For read cycles, pipelined

SRAM output data is temporarily stored by the edge triggered

output register during the access cycle and then released to the

output drivers at the next rising edge of clock.

The GS880Z18/36T is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 100-pin TQFP package.

GS880Z18/36T-11/100/80/66

2.5 V and 3.3 V V

100 MHz–66 MHz

Preliminary

3.3 V V

DDQ

Related parts for GS880Z18-100

GS880Z18-100 Summary of contents

Page 1

... Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off- chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS880Z18/36T may be configured by the user to operate -80 -66 in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered 12 ...

Page 2

... GS880Z18T Pinout 100 DDQ DDQ DDQ ...

Page 3

... Rev: 1.10 8/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com 256K x 36 Top View 3/25 Preliminary . GS880Z18/36T-11/100/80/ DDQ 76 ...

Page 4

... Pipeline/Flow Through Mode Control; active low 3.3 V output power supply for noise reduction - 4/25 Preliminary GS880Z18/36T-11/100/80/66 Description Address Inputs Address Input (x18 Version Only) Clock Input Signal -DQ ; active low A1 A9 -DQ ; active low B1 B9 -DQ ; active low (x32/x36 Versions Only) ...

Page 5

... GS880Z18/36 NBT SRAM Functional Block Diagram Rev: 1.10 8/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Amps Sense Drivers Write 5/25 Preliminary . GS880Z18/36T-11/100/80/66 © 1998, Giga Semiconductor, Inc. ...

Page 6

... and B ) determine which bytes will be written. All or none may be activated. A write cycle D 6/25 Preliminary GS880Z18/36T-11/100/80/ and Deassertion of any one of the Enable © 1998, Giga Semiconductor, Inc. . ...

Page 7

... External Next None Next Current None 7/25 Preliminary GS880Z18/36T-11/100/80/66 DQ Notes L-H High L-H High L-H High L-H High L L ...

Page 8

... and D represent input command codes as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipelined and Flow Through Read/Write Control State Diagram 8/25 Preliminary GS880Z18/36T-11/100/80/66 New Write Burst Write B D n+3 ƒ ƒ ...

Page 9

... and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 9/25 Preliminary GS880Z18/36T-11/100/80/66 Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 1998, Giga Semiconductor, Inc. . ...

Page 10

... and D represent input command Next State (n+1) n+1 n+2 ƒ ƒ Next State Pipelined and Flow Through Read Write Control State Diagram 10/25 Preliminary GS880Z18/36T-11/100/80/ Data Out W (Q Valid) D shown because it prevents any state change. codes as indicated in the Truth Tables. n+3 ƒ ...

Page 11

... Burst Sequence 10 11 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 11/25 Preliminary GS880Z18/36T-11/100/80/66 Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: ...

Page 12

... GSI NBT SRAMs are fully compatible with these sockets. Pin 66 Connect (NC) on GSI’s GS880Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36 NBT SRAM, is often marked as a power pin on other vendor’s NBT-compatible SRAMs. Specifically marked V pipelined parts and V on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ ...

Page 13

... Symbol Min. V 3.135 DD V 2.375 DDQ V 1 –0 – with a pulse width not to exceed 20% tKC. DD 13/25 Preliminary GS880Z18/36T-11/100/80/66 Unit Typ. Max. Unit 3 +0.3 — — ...

Page 14

... Overshoot Measurement and Timing 50% V Symbol Test conditions I/O OUT Layer Board Symbol R single JA R four JA R — JC 14/25 Preliminary GS880Z18/36T-11/100/80/66 20% tKC Typ. Max. Unit Max Unit Notes 40 C/W 1,2 24 C/W 1,2 9 C/W 3 © 1998, Giga Semiconductor, Inc. . ...

Page 15

... IN Output Disable OUT –8 mA 2.375 V OH DDQ I = –8 mA 3.135 V OH DDQ 15/25 Preliminary GS880Z18/36T-11/100/80/66 Output Load 2 2.5 V 225 DQ * 225 5pF Min Max – – –1 uA 300 uA –300 – – 1.7 V — ...

Page 16

... Flow-through Pipeline Flow-through Pipeline Flow-through 16/25 Preliminary GS880Z18/36T-11/100/80/66 -80 - -40 to +85°C 70°C +85°C 70°C +85°C 220 190 200 170 180 160 130 140 130 140 ...

Page 17

... Preliminary GS880Z18/36T-11/100/80/66 -80 -66 Unit Min Max Min Max 12.5 — 15 — ns — 4.8 — 1.5 — 1.5 — ns 1.5 — 1.5 — ns 15.0 — 20 — ns — 14.0 — ...

Page 18

... A3 A4 tKQ tKQX tLZ D D(A2) Q(A3) D(A1) (A2+ tOHZ BURST Read Read BURST Write Q(A3) Q(A4) Read D(A2+1) Q(A4+1) DON’T CARE = 18/25 Preliminary GS880Z18/36T-11/100/80/ tHZ tOE Q Q(A4) Q(A6) D(A5) (A4+1) tKQX tOLZ Write Read Write DESELECT D(A5) Q(A6) D(A7) UNDEFINED © 1998, Giga Semiconductor, Inc. . ...

Page 19

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com D(A1) Q(A2) Read STALL Read Write Q(A2) Q(A3) D(A4) DON’T CARE = 19/25 Preliminary GS880Z18/36T-11/100/80/ Q(A3) D(A4) Q(A5) tKQX NOP STALL Read CONTINUE DESELECT Q(A5) DESELECT UNDEFINED © 1998, Giga Semiconductor, Inc. . tHZ ...

Page 20

... tKQ tKQX tLZ D D(A2) Q(A3) Q(A4) (A2+1) tOHZ tH Write BURST Read Read BURST D(A2) Write Q(A3) Q(A4) Read D(A2+1) Q(A4+ 20/25 Preliminary GS880Z18/36T-11/100/80/ tOE tHZ Q Q(A6) D(A5) (A4+1) tKQX tOLZ Write Read Write DESELECT D(A5) Q(A6) D(A7) DON’T CARE UNDEFINED © 1998, Giga Semiconductor, Inc. . ...

Page 21

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Q(A2) D(A1) Q(A3) Read STALL Read Write STALL Q(A2) Q(A3) D(A4) DON’T CARE = 21/25 Preliminary GS880Z18/36T-11/100/80/ tHZ D(A4) Q(A5) tKQX NOP Read DESELECT CONTINUE Q(A5) DESELECT UNDEFINED © 1998, Giga Semiconductor, Inc. . ...

Page 22

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com 0 Out (Pull Down) VDDQ - V Out (Pull Up 22/25 Preliminary GS880Z18/36T-11/100/80/ Out VOut VS S 2.5 3 3 BPR 1999.05.18 © 1998, Giga Semiconductor, Inc. ...

Page 23

... Package width and length do not include mold protrusion. Rev: 1.10 8/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 22.0 22.1 e 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — — 0.10 — 7 23/25 Preliminary . GS880Z18/36T-11/100/80/ BPR 1999.05.18 © 1998, Giga Semiconductor, Inc. ...

Page 24

... GS880Z36T-11 256K x 36 GS880Z36T-100 256K x 36 GS880Z36T-80 256K x 36 GS880Z36T-66 512K x 18 GS880Z18T-11I 512K x 18 GS880Z18T-100I 512K x 18 GS880Z18T-80I 512K x 18 GS880Z18T-66I 256K x 36 GS880Z36T-11I 256K x 36 GS880Z36T-100I 256K x 36 GS880Z36T-80I 256K x 36 GS880Z36T-66I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS882Z36T-100IT. ...

Page 25

... GS880Z18/36T 1.05 9/ 1999K/ 1.06 10/1999 GS880Z18/36T 1.06 9/ 1999K 1.07 1/2000L GS880Z18/36T 1.07 1/ 2000K 1.08 5/2000M GS880Z18/36T 1.07 1/ 2000K 1.08 5/2000M; 880Z18_r1_09 880Z18_r1_09; 880Z18_r1_10 Rev: 1.10 8/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Page /Revisions/Reason • Last Page/Fixed “GSGS..” in Ordering Information Note.Document/Changed format of all E’ ...

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