GS88218AB GSI [GSI Technology], GS88218AB Datasheet - Page 9

• Manufacturer Part Number: GS88218AB
• Description: 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
• Manufacturer: GSI [GSI Technology]

Mode Pin Functions
Note:
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ and PE pins, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.04 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
1st address
3rd address
4th address
FLXDrive Output Impedance Control
Single/Dual Cycle Deselect Control
Output Register Control
Power Down Control
Burst Order Control
Mode Name
9th Bit Enable
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
11
00
10
00
01
11
11
00
01
10
Pin Name
9/38
SCD
LBO
ZQ
PE
ZZ
FT
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
2nd address
1st address
3rd address
4th address
H or NC
H or NC
H or NC
H or NC
L or NC
State
GS88218/36AB/D-250/225/200/166/150/133
H
H
L
L
L
L
L
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
Deactivate DQPx I/Os (x16/x32 mode)
Activate DQPx I/Os (x18/x36 mode)
High Drive (Low Impedance)
Low Drive (High Impedance)
Single Cycle Deselect
Dual Cycle Deselect
01
00
11
10
Standby, I
Interleaved Burst
Flow Through
Linear Burst
Function
Pipeline
Active
10
00
01
11
DD
© 2001, GSI Technology
= I
SB
11
10
01
00
BPR 1999.05.18
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