PSD913G2 STMICROELECTRONICS [STMicroelectronics], PSD913G2 Datasheet
PSD913G2
Related parts for PSD913G2
PSD913G2 Summary of contents
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FEATURES SUMMARY 5 V±10% Single Supply Voltage Mbit of Primary Flash Memory (8 uniform sectors) 256Kbit Secondary Flash Memory (4 uniform sectors Kbit SRAM Over 3,000 Gates of PLD: DPLD 52 Reconfigurable I/O ports ...
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The PSD9XX series of Programmable Microcontroller (MCU) Peripherals brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a Introduction simple and flexible solution for embedded designs. PSD9XX devices combine many of the peripheral functions found in ...
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PSD9XX Family 1.0 The PSD935G2 device offers two methods to program PSD Flash memory while the PSD is soldered to a circuit board. Introduction In-System Programming (ISP) via JTAG (Cont.) An IEEE 1149.1 compliant JTAG-ISP interface is included on the ...
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... Flash memory – 100,000 minimum • PLD – 1,000 minimum 3.0 PSD9XX Series Table 1. PSD9XX Product Matrix Part # PSD9XX I/O Series Device Pins Inputs Macrocells Macrocells Outputs PSD935G2 52 PSD9XX PSD913G2 27 PSD934F2 27 PLD Input Output PLD PSD9XX Family Flash Flash ...
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PLD INPUT BUS PAGE REGISTER CNTL0, CNTL1, PROG. CNTL2 MCU BUS INTRF AD0 – AD15 ADIO PORT 66 PROG. PORT PF0 – PF7 PORT F PROG. PORT PG0 – PG7 PORT G * Additional address lines can be ...
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PSD935G2 4.0 PSD9XX devices contain several major functional blocks. Figure 1 on page 3 shows the architecture of the PSD9XX device family. The functions of each block are described PSD9XX briefly in the following sections. Many of the blocks perform ...
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PSD9XX Family PSD9XX 4.5 ISP via JTAG Port Architectural In-System Programming can be performed through the JTAG pins on Port E. This serial interface allows complete programming of the entire PSD935G2 device. A blank device Overview can be completely programmed. ...
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PSD935G2 5.0 The PSD9XX series is supported by PSDsoft a Windows-based (95, 98, NT) software development tool. A PSD design is quickly and easily produced in a point and click Development environment. The designer does not need to enter Hardware ...
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PSD9XX Family 6.0 The following table describes the pin names and pin functions of the PSD935G2. Pins that have multiple names and/or functions are defined using PSD Configuration. Table 5. PSD935G2 Pin Descriptions Pin Name ADIO0-7 ADIO8-15 CNTL0 CNTL1 CNTL2 ...
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PSD935G2 Table 5. PSD935G2 Pin Pin Name Pkg.) Descriptions PA0-PA7 51-58 (cont.) PB0-PB7 61-68 PC0-PC7 41-48 PD0 PD1 PD2 PD3 PE0 PE1 PE2 Pin* (TQFP Type I/O Port A, PA0-7. This port is pin configurable and has multiple CMOS functions: ...
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PSD9XX Family Table 5. PSD935G2 Pin Pin Name Pkg.) Descriptions PE3 (cont.) PE4 PE5 PE6 PE7 PF0-PF7 PG0-PG7 21-28 GND Pin* (TQFP Type 74 I/O Port E, PE3. This port is pin configurable and has multiple CMOS ...
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PSD935G2 7.0 PSD935G2 Table 6 shows the offset addresses to the PSD935G2 registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the Register internal PSD935G2 registers. ...
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PSD9XX Family 8.0 All the registers in the PSD935G2 are included here for reference. Detail description of the registers are found in the Functional Block section of the Data Sheet. Register Bit Definition Data In Registers – Port A, B, ...
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PSD935G2 Flash Boot Protection Register 8.0 Register Bit Bit 7 Definition Security_Bit (cont.) Bit definitions: Sec<i>_Prot Sec<i>_Prot Security_Bit Page Register Bit 7 Pgr7 Bit definitions: Configure Page input to PLD. Default Pgr[7:0] = 00. PMMR0 Register Bit ...
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PSD9XX Family 8.0 VM Register Register Bit Bit 7 Definition * (cont.) Note: Upon reset, Bit1-Bit4 are loaded to configurations selected by the user in PSDsoft. Bit 0 is always cleared by reset. Bit 0 to Bit 4 are active ...
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PSD935G2 9.0 As shown in Figure 1, the PSD935G2 consists of six major types of functional blocks: The Memory Blocks PSD935G2 PLD Blocks Functional Bus Interface Blocks I/O Ports Power Management Unit JTAG-ISP Interface The functions of each block are ...
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PSD9XX Family The 9.1.1.2 Upper and Lower Block IN MAIN FLASH SECTOR PSD935G2 The PSD935G2’s main Flash has eight 64K bytes sector. The 64K byte sector size may cause some difficulty in code mapping for an 8-bit MCU with only ...
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PSD935G2 The 9.1.1.4 Memory Operation PSD935G2 The main Flash and secondary Flash memories are addressed through the microcontroller interface on the PSD935G2 device. The microcontroller can access these memories in one Functional of two ways: Blocks The microcontroller can execute ...
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PSD9XX Family The Table 9. Instructions PSD935G2 Functional Instruction Blocks Read (Note 5) (cont.) Read Main Flash ID (Notes 6,13) Read Sector Protection (Notes 6,8,13) Program a Flash Byte Erase One Flash Sector Erase Flash Block (Bulk Erase) Suspend Sector ...
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PSD935G2 The 9.1.1.5 Power-Up Condition PSD935G2 The PSD935G2 internal logic is reset upon power-up to the read array mode. The FSi and CSBOOTi select signals, along with the write strobe signal, must be in the false state Functional during power-up ...
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PSD9XX Family The 9.1.1.6.5 Data Polling Flag DQ7 PSD935G2 When Erasing or Programming the Flash memory bit DQ7 outputs the complement of the bit being entered for Programming/Writing on DQ7. Once the Program instruction or the Functional Write operation is ...
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PSD935G2 The 9.1.1.7 Programming Flash Memory PSD935G2 Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector. Flash memory sector erases to all logic ones (FF hex), Functional and its ...
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PSD9XX Family The Figure 4. Data Polling Flow Chart PSD935G2 Functional Blocks (cont.) 9.1.1.7.2 Data Toggle Checking the Data Toggle bit on DQ6 is a method of determining whether a Program or Erase instruction is in progress or has completed. ...
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PSD935G2 The 9.1.1.7.2 Data Toggle PSD935G2 It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed to compare the word that was written to Flash with Functional the word that ...
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PSD9XX Family The 9.1.1.8 Unlock Bypass Instruction PSD935G2 The unlock bypass feature allows the system to program words to the flash memories faster than using the standard program instruction. The unlock bypass instruction is Functional initiated by first writing two ...
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PSD935G2 The 9.1.1.9.3 Flash Erase Suspend Instruction PSD935G2 When a Flash Sector Erase operation is in progress, the Erase Suspend instruction will suspend the operation by writing 0B0h to any even address when an appropriate Chip Functional Select (FSi or ...
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PSD9XX Family The Table 10. Sector Protection/Security Bit Definition PSD935G2 Flash Protection Register Functional Bit 7 Blocks Sec7_Prot (cont.) Bit Definitions: Sec<i>_Prot Sec<i>_Prot Flash Boot Protection Register Bit 7 Security_ Bit *: Not used. Bit Definitions: Sec<i>_Prot Sec<i>_Prot Security_Bit 9.1.1.10.2 ...
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PSD935G2 The 9.1.2 SRAM PSD935G2 The SRAM is enabled when RS0— the SRAM chip select output from the DPLD— is high. RS0 can contain up to three product terms, allowing flexible memory mapping. Functional Blocks The SRAM can be backed ...
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PSD9XX Family The Figure 6. Priority Level of Memory and I/O Components PSD935G2 Functional Blocks (cont.) 9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces The 80C51 and compatible family of microcontrollers, can be configured to have ...
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PSD935G2 The 9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces PSD935G2 9.1.3.2.1 Separate Space Modes Functional Code memory space is separated from data memory space. For example, the PSEN Blocks signal is used to access the program ...
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PSD9XX Family The 9.1.4 Page Register PSD935G2 The eight bit Page Register increases the addressing capability of the microcontroller by a factor 256. The contents of the register can also be read by the microcontroller. Functional The ...
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PSD935G2 The 9.1.5 Memory ID Registers PSD935G2 The 8-bit read only memory status registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device by reading the Memory ID0 Functional and Memory ID1 ...
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PSD9XX Family The 9.2 PLDs PSD935G2 The PLDs bring programmable logic functionality to the PSD935G2. After specifying the logic for the PLDs in PSDsoft, the logic is programmed into the device and available upon Functional power-up. Blocks (cont.) The PSD935G2 ...
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PSD935G2 Figure 10. PLD Block Diagram 8 DATA BUS 66 GENERAL PURPOSE PLD 66 PAGE REGISTER 8 DECODE PLD GPLD PLD OUT 8 PLD OUT 8 PLD OUT 8 PORT A PLD INPUT 8 PORT B ...
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PSD9XX Family The 9.2.1 Decode PLD (DPLD) PSD935G2 The DPLD, shown in Figure 11, is used for decoding the address for internal components. The DPLD can generate the following decode signals: Functional • Blocks 8 sector selects for the main ...
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I /O PORTS (PORT A,B,C,F) (32) PGR0 -PGR7 (16 15 3:0 ] (ALE,CLKIN,CSI) PDN (APD OUTPUT) CNTRL [ 2 READ/WRITE CONTROL SIGNALS) RESET RD_BSY * NOTES: 1. The address inputs are ...
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PSD9XX Family Figure 12. The Micro Cell and I/O Port 36 BUS INPUT PLD PSD935G2 ...
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PSD935G2 The 9.3 Microcontroller Bus Interface PSD935G2 The “no-glue logic” PSD935G2 Microcontroller Bus Interface can be directly connected to most popular microcontrollers and their control signals. Key 8-bit microcontrollers with their Functional bus types and control signals are shown in ...
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PSD9XX Family The Figure 13. An Example of a Typical 8-Bit Multiplexed Bus Interface PSD935G2 Functional Blocks (cont.) MICRO- CONTROLLER RESET Figure 14. An Example of a Typical 8-Bit Non-Multiplexed Bus Interface CONTROLLER RESET 7 ...
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PSD935G2 The 9.3.3 Microcontroller Interface Examples Figures 15 through 19 show examples of the basic connections between the PSD935G2 PSD935G2 and some popular microcontrollers. The PSD935G2 Control input pins are labeled as to Functional the microcontroller function for which they ...
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PSD9XX Family The Table 15. 80C251 Configurations PSD935G2 Configuration Functional Blocks (cont.) 9.3.3.3 80C51XA The Philips 80C51XA microcontroller family supports 16-bit multiplexed bus that can have burst cycles. Address bits A[3:0] are not multiplexed, while A[19:4] are ...
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PSD935G2 Figure 15. Interfacing the PSD935G2 with an 80C31 19 X1 CRYSTAL RESET RESET 12 INT0 13 INT1 P1.0 2 P1.1 3 P1.2 4 P1.3 5 P1.4 6 P1.5 7 P1.6 8 ...
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PSD9XX Family Figure 16. Interfacing the PSD935G2 to the 80C251, with One Read Input U1 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 CRYSTAL P3.0/RXD 13 P3.1/TXD ...
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PSD935G2 Figure 17. Interfacing the PSD935G2 to the 80C251, with Read and PSEN Inputs 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 CRYSTAL P3.0/RXD 13 P3.1/TXD 14 ...
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PSD9XX Family Figure 18. Interfacing the PSD935G2 to the 80C51XA, 8-Bit Data Bus 21 XTAL1 CRYSTAL 20 XTAL2 11 RXD0 13 TXD0 6 RXD1 7 TXD1 9 T2EX RESET 10 RST 14 INT0 15 INT1 V ...
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PSD935G2 Figure 19. Interfacing the PSD935G2 with a 68HC11 34 PA0 33 PA1 32 PA2 31 PA3 30 PA4 29 PA5 28 PA6 27 PA7 8 XT CRYSTAL IRQ 18 XIRQ 20 PD0 21 PD1 22 PD2 ...
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PSD9XX Family The 9.4 I/O Ports PSD935G2 There are seven programmable I/O ports: Ports and G. Each of the ports is eight bits except Port D, which is 4 bits. Each port pin is ...
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PSD935G2 The Table 16. Port Operating Modes PSD935G2 Port Mode Functional MCU I/O Blocks PLD Outputs (cont.) PLD Inputs Address Out Address In Data Port JTAG ISP Figure 20. General I/O Port Architecture PSD9XX Family Port A Port B Port ...
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PSD9XX Family Table 17. Port Operating Mode Settings The PSD935G2 Functional Blocks Mode (cont.) MCU I/O PLD I/O Data Port (Port F) Address Out (Port Address In (Port A,B,C,D,F) JTAG ISP * NA = Not Applicable NOTE: ...
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PSD935G2 The 9.4.2.3 Address Out Mode PSD935G2 For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used to drive latched addresses onto the port pins. These port pins can, in turn, drive external Functional devices. Either the ...
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PSD9XX Family The 9.4.3 Port Configuration Registers (PCRs) PSD935G2 Each port has a set of PCRs used for configuration. The contents of the registers can be accessed by the microcontroller through normal read/write bus cycles at the addresses Functional given ...
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PSD935G2 The 9.4.3.3 Drive Select Register PSD935G2 The Drive Select Register configures the pin driver as Open Drain or CMOS for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should Functional ...
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PSD9XX Family The 9.4.5 Ports A, B and C – Functionality and Structure PSD935G2 Ports A and B have similar functionality and structure, as shown in Figure 21. The two ports can be configured to perform one or more of ...
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PSD935G2 The 9.4.6 Port D – Functionality and Structure PSD935G2 Port D has four I/O pins. See Figure 22. Port D can be configured to program one or more of the following functions: Functional Blocks MCU I/O Mode (cont.) PLD ...
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PSD9XX Family The 9.4.8 Port F – Functionality and Structure PSD935G2 Port F can be configured to perform one or more of the following functions: Functional MCU I/O Mode Blocks PLD Input – as direct input ot the PLD array. ...
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PSD935G2 The 9.5 Power Management PSD935G2 The PSD935G2 offers configurable power saving options. These options may be used individually or in combinations, as follows: Functional Blocks All memory types in a PSD (Flash, Secondary Flash, and SRAM) are built with ...
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PSD9XX Family The 9.5.1 Automatic Power Down (APD) Unit and Power Down Mode (cont.) PSD935G2 Power Down Mode Functional By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled. Blocks The device will enter Power ...
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PSD935G2 The Figure 24. APD Logic Block PSD935G2 Functional Blocks APD EN PMMR0 BIT 1=1 (cont.) ALE RESET CSI CLKIN Figure 25. Enable Power Down Flow Chart TRANSITION DETECTION CLR PD APD COUNTER EDGE PD DETECT DISABLE MAIN AND SECONDARY ...
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PSD9XX Family The Table 26. Power Management Mode Registers (PMMR0, PMMR2)** PSD935G2 PMMR0 Functional Bit 7 Blocks * (cont.) *** Bits and 7 are not used, and should be set to 0, bit 5 should be set ...
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PSD935G2 The Table 27. APD Counter Operation PSD935G2 APD Functional Enable Bit Blocks 0 (cont 9.5.2 Other Power Saving Options The PSD935G2 offers other reduced power saving options that are independent of the Power Down Mode. Except ...
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PSD9XX Family The 9.5.3 Reset and Power On Requirement PSD935G2 9.5.3.1 Power On Reset Functional Upon power up the PSD935G2 requires a reset pulse of tNLNH-PO (minimum 1 ms) after Blocks V is steady. During this time period the device ...
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PSD935G2 The Table 28. Status During Power On Reset, Warm Reset and Power Down Mode PSD935G2 Port Configuration Functional MCU I/O Blocks PLD Output (cont.) Address Out Data Port Register PMMR0 Register* All other registers * SR_cod bit ...
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PSD9XX Family The 9.6.1 Standard JTAG Signals PSD935G2 The JTAG configuration bit (non-volatile) inside the PSD can be set by the user in the PSDsoft. Once this bit is set and programmed in the PSD, the JTAG pins are dedicated ...
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PSD935G2 10.0 Symbol Absolute T STG Maximum Ratings NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device ...
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PSD9XX Family AC/DC The following tables describe the AD/DC parameters of the PSD9XX family: Parameters DC Electrical Specification AC Timing Specification • PLD Timing – Combinatorial Timing • Microcontroller Timing – Read Timing – Write Timing – Power Down and ...
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PSD935G2 AC/DC Figure 27a. PLD I Parameters (cont.) Example of PSD935G2 Typical Power Calculation at V Conditions Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash Access % SRAM access % I/O access Operational Modes ...
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PSD9XX Family AC/DC Example of Typical Power Calculation at V Parameters Conditions (cont.) Highest Composite PLD input frequency MCU ALE frequency (Freq ALE) Operational Modes Number of product terms used Turbo Mode Calculation (typical numbers used) I total = Ipwrdown ...
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PSD935G2 PSD935G2 DC Characteristics Symbol Parameter V Supply Voltage CC V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis ...
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PSD9XX Family Microcontroller AC Symbols for PLD Timing. Interface – Example: AC/DC Parameters Signal Letters (5V ± 10% Versions) A – Address Input C – CEout Output D – Input Data E – E Input I – Interrupt Input L ...
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PSD935G2 Microcontroller Interface – PSD935G2 AC/DC Parameters (5V ± 10% Versions) Read Timing (5 V ± 10% Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid ...
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PSD9XX Family Microcontroller Interface – PSD935G2 AC/DC Parameters (5V ± 10% Versions) Write Timing (5 V ± 10% Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX Address Valid ...
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PSD935G2 Microcontroller Interface – PSD935G2 AC/DC Parameters (5V ± 10% Versions) Power Down Timing (5 V ± 10%) Symbol Parameter ALE Access Time from t LVDV Power Down Maximum Delay from APD Enable t to Internal PDN Valid Signal CLWH ...
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PSD9XX Family Microcontroller Interface – PSD935G2 AC/DC Parameters (5V ± 10% Versions) Flash Program, Write and Erase Times Symbol Parameter Flash Program Flash Bulk Erase (Preprogrammed to 00) (Note 1) Flash Bulk Erase t Sector Erase (Preprogrammed to 00) WHQV3 ...
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PSD935G2 PSD935G2 DC Characteristics Symbol Parameter V Supply Voltage CC V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis ...
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PSD9XX Family Microcontroller AC Symbols for PLD Timing. Interface – Example: PSD935G2 AC/DC Signal Letters Parameters A – Address Input C – CEout Output (3 3.6 V Versions) D – Input Data E – E Input L – ...
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PSD935G2 Microcontroller Interface – PSD935G2 AC/DC Parameters (3 3.6 V Versions) Read Timing (3 3.6 V Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX ...
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PSD9XX Family Microcontroller Interface – PSD935G2 AC/DC Parameters (3 3.6 V Versions) Write Timing (3 3.6 V Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time ...
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PSD935G2 Microcontroller Interface – PSD935G2 AC/DC Parameters (3 3.6 V Versions) Power Down Timing (3 3.6 V Versions) Symbol Parameter ALE Access Time from t LVDV Power Down Maximum Delay from APD Enable t CLWH to ...
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PSD9XX Family Microcontroller Interface – PSD935G2 AC/DC Parameters (3 3.6 V Versions) Flash Program, Write and Erase Times Symbol Parameter Flash Program Flash Bulk Erase (Preprogrammed to 00) (Note 1) Flash Bulk Erase t Sector Erase (Preprogrammed to ...
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PSD935G2 Figure 28. Read Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS AVPV * t and t are not required 80C51XA in Burst Mode. AVLX LXAX * t AVLX ...
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PSD9XX Family Figure 29. Write Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL t WLWH t ...
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PSD935G2 Figure 30. Combinatorial Timing – PLD GPLD INPUT GPLD OUTPUT Figure 31. JTAG-ISP Timing TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO ISCCH t ISCCL t t ISCPSU ISCPH PSD9XX Family t ISCPZV t ISCPCO t ISCPVZ 81 ...
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PSD9XX Family Figure 32. Reset Timing OPERATING LEVEL V CC RESET Figure 33. Key to Switching Waveforms WAVEFORMS 82 t NLNH– OPR POWER ON RESET INPUTS STEADY INPUT MAY CHANGE FROM MAY CHANGE FROM LO ...
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PSD935G2 14 ° MHz A Pin Capacitance Symbol OUT C VPP NOTES: 1. These parameters are only sampled and are not 100% tested. 2. Typical values are for T 15.0 Figure ...
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PSD9XX Family 18.0 80-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) PSD935G2 Pin No. Pin Assignments ...
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PSD935G2 19.0 Figure 36. Drawing U5 – 80-Pin Plastic Thin Quad Flatpack (TQFP) PSD935G2 Package Information PD2 PD3 AD0 AD1 AD2 AD3 AD4 GND V CC AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 (Package Type U) ...
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PSD9XX Family Figure 36A. Drawing U5 – 80-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type Index 3 Mark B Family: Plastic Thin Quad Flatpack (TQFP) Symbol Min 0° A – A2 0.95 B ...
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Selector Guide – PSD935G2 Series Part # MCU PLDs/Decoders 5 Data Inputs Input Macrocells Path Volts Output Macrocells Outputs Page Reg. PSD935G2 8 52 – – 24 8-bit PSD913F2 8 27 – 8-bit PSD934F2 8 27 – _ ...
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PSD9XX Family 21.0 Flash PSD Part Number Construction Part Number CHARACTER # 1 Construction PART NUMBER PSD BRAND NAME PSD = Standard Low Power Device FAMILY/SERIES 8 = Flash PSD for 8-bit MCUs 9 = Flash PSD for 8-bit MUCs ...
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PSD935G2 REVISION HISTORY Table 1. Document Revision History Date Rev. 25-Feb-2000 1.0 PSD935G2: Document written in the WSI format. Initial release Specifications changed tLXAX -70 Min from Page 70: changed Turbo Off from add 10 to add ...
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. ...