ISL6740 INTERSIL [Intersil Corporation], ISL6740 Datasheet
ISL6740
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ISL6740 Summary of contents
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... Data Sheet Flexible Double Ended Voltage and Current Mode PWM Controllers The ISL6740, ISL6741 family of adjustable frequency, low power, pulse width modulating (PWM) voltage mode (ISL6740) and current mode (ISL6741) controllers is designed for a wide range of power conversion applications using half-bridge, full bridge, and push-pull configurations. ...
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... OT SHUTDOWN BI-DIRECTIONAL +130°C TO +150°C SYNCHRONIZATION SYNC IN INHIBIT/VIN UV 1.00V + EXT. SYNC INHIBIT UV - IRTC OSCILLATOR RTC IRTD RTD CLK SCSET SHORT CIRCUIT DETECTION CT CS 0.6V 0.4 VERROR 0.4 OTS ISL6740 SYNC 100 4.5k SS LOW - + 4.5V SS CLAMP SS DONE OC DETECT + - S R PWM COMPARATOR PWM LATCH + RESET - - DOMINANT SS 0.5 VREF ...
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Functional Block Diagram (Continued) VREF VDD VREF 5. ENABLE + - + - BG GND N_SYNC OUT INTERNAL OT SHUTDOWN BI-DIRECTIONAL +130°C TO +150°C SYNCHRONIZATION INHIBIT/VIN UV 1. EXT. SYNC INHIBIT UV - IRTC OSCILLATOR RTC ...
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... Typical Application (ISL6740) - 48V Input DC Transformer, 12V @ 8A Output (ISL6740EVAL1) VIN CR3 VIN- R7 TP6 C13 R10 TP1 T2 QL C14 R11 CR2 CR1 TP4 HIP2101 VDD LO HB VSS RT1 TP5 U3 GND OUTB OUTA R17 V DD ...
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... Typical Application (ISL6740) - 36V to 75V Input, Regulated 12V @ 8A Output (ISL6740EVAL2Z) VIN CR3 36V TO 75V VIN- R7 TP6 Q5 D1 R26 CR5 C13 R10 TP1 T2 CR6 R27 QL C14 R11 CR2 CR1 R14 R5 U1 TP4 HIP2101 VDD LO HB VSS RT1 ...
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Typical Application (ISL6741) - 48V to 5V Push-Pull DC/DC Converter +48V C1 Q1 SYNC R2 R1 VIN VR1 + 5V QR1 R18 T1 EL7242 QR2 U5 RT1 Q2 R12 R11 R3 GND VERROR OUTB CS ...
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... Charged Device Model (Per EOS/ESD DS5.3, 4/14/93 .1000V Operating Conditions Temperature Range ISL6740Ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C ISL6741Ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C Supply Voltage Range (Typical 9VDC - 16VDC CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. 1. θ ...
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... PWM Comparator Input Offset ERROR (ISL6741 PWM Comparator Input Gain (ISL6741) (Note 4) ERROR V to PWM Comparator Input Gain (ISL6740) (Note 4) ERROR C to PWM Comparator Input Gain (ISL6740 PWM Comparator Input Gain (ISL6740 PWM Comparator Input Gain (ISL6741) OSCILLATOR ...
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... This parameter, although guaranteed by characterization or correlation testing, is not 100% tested in production. 5. SYNC pulse width is the greater of this value or the C 6. This is the maximum duty cycle achievable using the specified values of R obtained using other values for these components. See Equations 2 through 4. 9 ISL6740, 1SL6741 < 51.1kΩ 10kΩ ...
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... Synchronization may be achieved by connecting the SYNC signal of each unit together or by using an external master clock signal. The oscillator timing capacitor, C required regardless of the synchronization method used. The paralleled unit with the highest oscillator frequency assumes control. 10 ISL6740, 1SL6741 110 FIGURE 2. OSCILLATOR C 70 ...
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... SCSET to GND disables short circuit shutdown and hiccup. Functional Description Features The ISL6740, ISL6741 PWMs are an excellent choice for low cost bridge and push-pull topologies for applications requiring accurate duty cycle and deadtime control. With its many protection and control features, a highly flexible design with minimal external components is possible ...
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... Fault during soft-start. Gate Drive The ISL6740, ISL6741 are capable of sourcing and sinking 0.5A peak current, but are primarily intended to be used in conjunction with a MOSFET driver due to the 5V drive level. To limit the peak current through the IC, an external resistor (EQ ...
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... DOWN Over Current Operation ISL6740 - Overcurrent delayed shutdown is enabled once the soft-start cycle is complete overcurrent condition is detected, the soft-start charging current source is disabled and the soft-start capacitor is allowed to discharge through a 15μA source. At the same time a 50μs re-triggerable one- shot timer is activated. It remains active for 50μ ...
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... A good ground plane must be employed bypassed directly to GND with good high frequency capacitance. Typical Application The Typical Application Schematic features the ISL6740 in an unregulated half-bridge DC/DC converter configuration, often referred Transformer or Bus Regulator. The ISL6740EVAL1 demonstration unit implements this design and is available for evaluation ...
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... Select core size. Core size will be dictated by the capability of the core structure to store the required 15 ISL6740, 1SL6741 energy, the number of turns that have to be wound, and the wire gauge needed. Often the window area (the space used for the windings) and power loss determine the final core size. • ...
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... Converting c.m. to square 2 mils yields 555mils (0.785 sq. mils/c.m.). Dividing by the 16 ISL6740, 1SL6741 trace width results in a copper thickness of 4.44 mils (0.112mm). Using 1.3 mils/oz. of copper requires a copper weight of 3.4oz. For reasons of cost, 3oz. copper was selected. One layer of each secondary winding also contains the synchronous rectifier winding ...
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... FIGURE 7A. TOP LAYER: 1 TURN SECONDARY AND SR WINDINGS FIGURE 7B. INT. LAYER 1: 1 TURN SECONDARY WINDING FIGURE 7C. INT. LAYER 2: 2 TURNS PRIMARY WINDING 17 ISL6740, 1SL6741 FIGURE 7D. INT. LAYER 3: 2 TURNS PRIMARY WINDING FIGURE 7E. INT. LAYER 4: 1 TURN SECONDARY WINDING FIGURE 7F. BOTTOM LAYER: 1 TURN SECONDARY AND SR WINDINGS ∅ ...
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... DS(ON) find in a 60V device. It was decided to use two devices in parallel to simplify the thermal design. Two Fairchild FDS5670 18 ISL6740, 1SL6741 devices are used in parallel for a total of four SR FETs. The FDS5670 is rated at 60V and 10A (r Oscillator Component Selection The desired operating frequency of 235kHz for the converter was established in the Design Criteria section ...
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... The current level that corresponds to the overcurrent threshold must be chosen to allow for the dynamic behavior 19 ISL6740, 1SL6741 of an open loop converter. In particular, the low inductor ripple current under steady state operation increases significantly as the duty cycle decreases. ...
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... As expected, the output voltage varies considerably with line and load when compared to an equivalent converter with closed loop feedback. However, for applications where tight 20 ISL6740, 1SL6741 regulation is not required, such as those application that use downstream DC/DC converters, this design approach is viable. Waveforms (EQ ...
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... FIGURE 15. FET DRAIN-SOURCE VOLTAGE FIGURE 16. FET D-S VOLTAGE NEAR-ZVS TRANSITION FIGURE 17. OUTA TO OUTB TRANSITION 21 ISL6740, 1SL6741 Component List REFERENCE DESIGNATOR VALUE C 1.0μ 3.3μ 1.0μ 0.1μ Open 7 C 22μ 150μ 1000pF Capacitor, 0603, X7R, 50V, 10% ...
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... Adding Regulation - Closed Loop Feedback 100k The second Typical Application schematic adds closed loop feedback with isolation. The ISL6740EVAL2Z demonstration platform implements this design and is available for evaluation. The input voltage range was increased to 36V to 75V, which necessitates a few modifications to the open loop design. The output inductor value was increased to 4.0μ ...
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... L = Output Inductance C = Output Capacitance R = Output Capacitance ESR Sawtooth Ramp Amplitude S Gain and phase plots of (Equation 26) appear below using L = 4.0μ 150μ 28mΩ 1.2Ω, and VIN = 75V. 23 ISL6740, 1SL6741 V OUT - REF V OUT The Type 3 compensation configuration has three poles and two zeros ...
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... FREQUENCY (Hz) FIGURE 22A. OPTO COUPLER GAIN -45 - 100 1•10 1•10 FREQUENCY (Hz) FIGURE 22B. OPTO COUPLER 24 ISL6740, 1SL6741 The following compensation components were selected R = 9.53kΩ the switching R = 2.49kΩ 499Ω 4.22kΩ 1nF ...
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... FREQUENCY (Hz) FIGURE 24B. EA PLUS OPTO COUPLER GAIN 25 ISL6740, 1SL6741 Using the control-to-output transfer function combined with the EA transfer function, the loop gain and phase may be predicted. The predicted loop gain and phase margin of the converter appear in Figures 25A and 25B: ...
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... The actual loop gain and phase margin measured on the ISL6740EVAL2Z demonstration board appear in Figures 26A and 26B -10 -20 -30 -40 -50 0.1k 1k FREQUENCY (Hz) FIGURE 26A. MEASURED LOOP GAIN 225 180 135 -45 -90 -135 0.1k 1k FREQUENCY (Hz) FIGURE 26B. MEASURE LOOP PHASE MARGIN ...
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... Resistor, 2512 10.0 Resistor, 0603 499 Resistor, 0603 2.20 Resistor, 0805 200 Resistor, 0603 75.0k Resistor, 0805 ISL6740, 1SL6741 Component List REFERENCE DESIGNATOR VALUE 205 11 R 8.06k 12 R 18. Open 14 R 1.27k ...
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... Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. (Angles in degrees) 28 ISL6740, 1SL6741 M16.173 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 29 ISL6740, 1SL6741 M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE ...