EDD1232AABH ELPIDA [Elpida Memory], EDD1232AABH Datasheet
EDD1232AABH
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EDD1232AABH Summary of contents
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... DDR SDRAM EDD1232AABH (4M words 32 bits) Description The EDD1232AABH is a 128M bits DDR SDRAM organized as 1,048,576 words 32 bits Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design ...
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... Organization 32: x32 Power Supply, Interface A: 2.5V, SSTL_2 Die Rev. Package BH: FBGA Speed 6B: DDR333B (2.5-3-3) 7A: DDR266A (2-3-3) Environment Code E: Lead Free Data Sheet E0533E50 (Ver. 5.0) Internal Data Rate JEDEC speed bin bits) banks Mbps (max.) (CL-tRCDRD-tRP) 333 DDR333B (2.5-3-3) 4 266 DDR266A (2-3-3) 2 EDD1232AABH Package 144-ball FBGA ...
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... A11 A9 A5 RFU (Top view) Pin name CK /CK CKE VREF VDD VSS VDDQ VSSQ MCL RFU* 3 EDD1232AABH VSSQ DM3 DQS3 NC VDDQ DQ27 VSSQ DQ26 DQ25 VDD VDDQ DQ24 VDDQ DQ15 DQ14 VDDQ DQ13 DQ12 NC DM1 DQS1 VDDQ DQ11 DQ10 ...
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... CONTENTS Description.....................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Pin Configurations .........................................................................................................................................3 Electrical Specifications.................................................................................................................................5 Block Diagram .............................................................................................................................................11 Pin Function.................................................................................................................................................12 Command Operation ...................................................................................................................................14 Simplified State Diagram .............................................................................................................................21 Operation of the DDR SDRAM ....................................................................................................................22 Timing Waveforms.......................................................................................................................................41 Package Drawing ........................................................................................................................................47 Recommended Soldering Conditions..........................................................................................................48 Data Sheet E0533E50 (Ver. 5.0) EDD1232AABH 4 ...
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... +70 Tstg –55 to +125 min. typ. 2.3 2 0.49 VDDQ 0.50 VDDQ VREF – 0.04 VREF VREF + 0.15 — –0.3 — –0.3 — 0.5 VDDQ 0.2V 0.5 VDDQ 0.36 — 5 EDD1232AABH Unit Note max. Unit Notes 2 0.51 VDDQ V VREF + 0.04 V VDDQ + 0 VREF – 0. VDDQ + 0 ...
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... 375 max. Unit Test condition 2 µA VDD ≥ VIN ≥ VSS 5 µA VDDQ ≥ VOUT ≥ VSS — mA VOUT = 1.95V — mA VOUT = 0.35V 6 EDD1232AABH Notes Notes ...
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... EDD1232AABH max. Unit Notes 6 VOUT = 0.2V, max. Unit Notes 0.55 tCK 0.55 tCK — tCK — ...
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... EDD1232AABH max. Unit Notes — ns — ns — ns — — ns — ns — tCK — tCK 7.8 µs ...
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... VTT VREF VIH (AC) VREF 0.31 VIL (AC) VREF 0.31 VID (AC) 0.62 VIX (AC) VREF SLEW 1 tCK tCL tCH VIX VDD VIH VREF VIL VSS t SLEW = (VIH (AC) – VIL (AC))/ t VTT 30pF Input Waveforms and Output Load 9 EDD1232AABH Unit V/ns VDD VREF VSS ...
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... EDD1232AABH max. Unit tCK tCK tCK tCK tCK tCK 2 tCK 2.5 tCK 3 tCK tCK tCK tCK 2 tCK 2.5 tCK 3 tCK 1 tCK tCK 0 tCK tCK tCK ...
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... Data Sheet E0533E50 (Ver. 5.0) Bank 1 Row address Memory cell array buffer Bank 0 and refresh counter Sense amp. Column decoder Column address buffer and burst Data control circuit counter Latch circuit DLL CK, /CK Input & Output buffer DQ 11 EDD1232AABH Bank 3 Bank 2 DQS DM ...
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... BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table] BA0 Bank 0 L Bank 1 H Bank 2 L Bank 3 H Remark: H: VIH. L: VIL. Data Sheet E0533E50 (Ver. 5.0) EDD1232AABH Column address AY0 to AY7 BA1 ...
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... VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. MCL (input pins) This pin must be connected with VSS. A connection with any level other than VSS may result in undefined operation. Data Sheet E0533E50 (Ver. 5.0) EDD1232AABH DQs DQ0 to DQ7 DQ8 to DQ15 DQ16 to DQ23 DQ24 to DQ31 ...
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... L H PRE PALL REF SELF MRS EMRS EDD1232AABH BA1 BA0 AP Address ...
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... Power down Power down exit (PDEX) Remark: H: VIH. L: VIL. : VIH or VIL. Notes: 1. All the banks must be in IDLE before executing this command. 2. The CKE level must be kept for 1 CK cycle at least. Data Sheet E0533E50 (Ver. 5.0) EDD1232AABH BA1 CKE n – 1 ...
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... ILLEGAL DESL NOP NOP NOP BST ILLEGAL BA, CA, A8 READ/READA Starting read operation Read/READA BA, CA, A8 WRIT/WRITA Starting write operation BA, RA ACT ILLEGAL* BA, A8 PRE, PALL Pre-charge ILLEGAL 16 EDD1232AABH Next state ldle ldle 11 — 11 — 11 — 11 — ldle — ldle ldle 11 — 11 — 11 — ...
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... NOP NOP NOP BST ILLEGAL BA, CA, A8 READ/READA Starting read operation. Read/ReadA Starting new write BA, CA, A8 WRIT/WRITA operation. BA, RA ACT ILLEGAL* BA, A8 PRE/PALL ILLEGAL* ILLEGAL 17 EDD1232AABH Next state Active Active Active Active 13 — 11 — Precharging — Precharging Precharging — 14 — 14 — 11, 14 — ...
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... READ/READA ILLEGAL* BA, CA, A8 WRIT/WRIT A ILLEGAL* BA, RA ACT ILLEGAL* BA, A8 PRE, PALL ILLEGAL* ILLEGAL Minimum delay (Concurrent AP supported) BL/2 CL(rounded up)+ (BL/ (BL/2) + tWTR BL EDD1232AABH Next state Precharging Precharging — 14 — 14 — 11, 14 — 11, 14 — — Units tCK tCK tCK tCK tCK tCK ...
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... OPCODE Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table H Refer to operations in Function Truth Table L H Self refresh L L OPCODE Refer to operations in Function Truth Table Power down Refer to operations in Function Truth Table Power down 19 EDD1232AABH Notes Idle ...
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... DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command within 7.8 s. Power down exit [PDEX] The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued. Data Sheet E0533E50 (Ver. 5.0) EDD1232AABH 20 ...
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... Data Sheet E0533E50 (Ver. 5.0) SELF REFRESH SR ENTRY SR EXIT *1 MRS REFRESH AUTO IDLE REFRESH CKE CKE_ IDLE ACTIVE POWER CKE_ DOWN CKE ROW ACTIVE BST READ WRITE READ Read WITH WITH AP AP READ READ READ WITH AP READ WITH AP PRECHARGE READA PRECHARGE PRECHARGE PRECHARGE 21 EDD1232AABH ...
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... RP RFC 200 cycles (min LMODE BT A3 Burst Type Sequential 0 2.5 1 Interleave EDD1232AABH (9) Any MRS command t 2 cycles (min.) RFC Disable DLL reset with A8 = Low Burst Length BT=0 BT ...
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... EDD1232AABH A1 A0 DLL A0 DLL Control 0 DLL Enable 1 DLL Disable Interleave ...
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... Data Sheet E0533E50 (Ver. 5.0) tCK + tAC (ns) after the clock rising READ NOP Column tRPRE out0 out1 out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 Read Operation (Burst Length) 24 EDD1232AABH t8 t9 tRPST BL: Burst length ...
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... WRITE NOP Column tWPREH tWPRES in0 in1 tWPST in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 Write Operation 25 EDD1232AABH t4 t4.5 t5 t5.5 tRPST VTT VTT tRPST VTT VTT out3 tRPST VTT VTT out2 out3 t8 t9 in6 in7 BL: Burst length ...
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... CK /CK Command READ DQS DQS CL = 2.5 DQ DQS Burst Stop during a Read Operation Data Sheet E0533E50 (Ver. 5.0) t1 t1.5 t2 t2.5 t3 t3.5 BST NOP tBSTZ 2 cycles out0 out1 tBSTZ 2.5 cycles out0 out1 tBSTZ out0 out1 26 EDD1232AABH t4 t4.5 t5 t5.5 3 cycles CL: /CAS latency ...
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... Note: Internal auto-precharge starts at the timing indicated by " Data Sheet E0533E50 (Ver. 5.0) Refer to ‘Function truth table and related tRPD 2 cycles (= BL/2) READA NOP tAC,tDQSCK out0 out1 out2 ". Read with auto-precharge NOP BL cycles in1 in2 in3 in4 ". Burst Write ( EDD1232AABH tRP (min) ACT out3 tRP ACT ...
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... ACT command. tRCDRD after the ACT command, the consecutive read command can be issued READ READ Column B out out out out Column = B Read Column = A Column = B Dout Dout 28 EDD1232AABH NOP out out Bank0 ...
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... READ to READ Command Interval (different bank) Data Sheet E0533E50 (Ver. 5. READ READ NOP Column A Column B out out A0 A1 Column = A Column = B Read Read Bank0 Dout Bank0 Bank3 Read Read 29 EDD1232AABH t8 t9 NOP out out out out Bank3 Dout ...
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... Precharge the bank without interrupting the preceding write operation. tRP after the precharge command, issue the ACT command. tRCDWR after the ACT command, the consecutive write command can be issued. tn+1 tn+2 tn+3 tn+4 WRIT Column B inA0 inA1 inB0 inB1 inB2 inB3 Column = A Column = B Write Write 30 EDD1232AABH tn+5 tn+6 NOP Bank0 ...
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... ACT NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active WRITE to WRITE Command Interval (different bank) Data Sheet E0533E50 (Ver. 5.0) tn tn+1 tn+2 NOP WRIT WRIT Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Bank3 Write Write 31 EDD1232AABH tn+3 tn+4 tn+5 NOP Bank0, 3 ...
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... Precharge the bank independently of the preceding read operation. tRP after the precharge command, issue the ACT command. tRCDWR after the ACT command, the consecutive write command can be issued WRIT out0 out1 in0 in1 in2 in3 INPUT READ to WRITE Command Interval 32 EDD1232AABH NOP ...
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... Precharge the bank independently of the preceding write operation. tRP after the precharge command, issue the ACT command. tRCDRD after the ACT command, the consecutive read command can be issued NOP READ tWTR* in3 WRITE to READ Command Interval 33 EDD1232AABH NOP out0 out1 out2 out3 OUTPUT ...
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... DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command not necessary. 1 — NOP out0 out1 out2 out3 in2 34 EDD1232AABH High-Z High CL= 2 ...
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... Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. [WRITE to READ delay = 4 clock cycle] Data Sheet E0533E50 (Ver. 5. NOP CL=2 in2 in3 out0 out1 out2 out3 READ CL=2 tWTR* in2 in3 35 EDD1232AABH High-Z High CL NOP out0 out1 out2 out3 CL= 2 ...
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... READ to PRECHARGE Command Interval (same bank): To output all data ( Data Sheet E0533E50 (Ver. 5. PRE/ NOP PALL out0 out1 out2 out3 PRE/ NOP PALL out0 out1 out2 out3 PRE/ NOP PALL out0 out1 out2 out3 36 EDD1232AABH ...
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... READ to PRECHARGE Command Interval (same bank): To stop output data ( Data Sheet E0533E50 (Ver. 5. NOP PRE/PALL out0 out1 tHZP PRE/PALL NOP CL = 2.5 out0 out1 tHZP PRE/PALL NOP out0 out1 tHZP 37 EDD1232AABH t7 t8 High-Z High High-Z High High-Z High-Z ...
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... Command WRIT DM DQS DQ in0 in1 Precharge Termination in Write Cycles (same bank) ( Data Sheet E0533E50 (Ver. 5. NOP tWPD tWR in2 in3 Last data input NOP PRE/PALL tWR in2 in3 Data masked 38 EDD1232AABH t6 t7 PRE/PALL NOP t6 t7 NOP ...
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... ACT command, the next ACT command can be issued. ACT NOP PRE ROW: 1 Bank3 Bank0 Active Precharge tRC Bank Active to Bank Active NOP ACT BS and ROW Bank3 Active tMRD 39 EDD1232AABH NOP ACT NOP ROW: 0 Bank0 Active NOP ...
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... DM can mask input data. By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function DQS DQ DM Data Sheet E0533E50 (Ver. 5. Mask Mask Write mask latency = 0 DM Control 40 EDD1232AABH t5 t6 ...
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... Data Sheet E0533E50 (Ver. 5.0) tIS tIH tIS tIH tDQSCK tDQSCK tDQSCK tDQSQ tQH tLZ tAC tAC tDQSQ tQH tDSS tDSH tDQSL tDQSH tDIPW tDH tDH tDIPW 41 EDD1232AABH VREF VREF tDQSCK tRPST tDQSQ tQH tAC tHZ tDQSQ tQH tDSS VREF tWPST VREF VREF tDIPW ...
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... Bank 0 Bank 0 Bank 0 Read Read Precharge 42 EDD1232AABH tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tRPST Bank0 Access = VIH or VIL ...
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... Data Sheet E0533E50 (Ver. 5.0) tRC tRAS tDQSS tDQSL tWPST tDQSH tDS tDS tDS tDH tWR tDH 43 EDD1232AABH tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH ...
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... Data Sheet E0533E50 (Ver. 5. tMRD Bank 3 Bank 3 Bank 3 Read Precharge Active R:b C tRWD Bank 3 Bank 3 Active Write 44 EDD1232AABH VIH or VIL C:b'' b’’ tWRD Bank 3 Read Read cycle =VIH or VIL ...
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... Auto Refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A8=1 DM DQS DQ (output) DQ (input) tRP Precharge If needed Data Sheet E0533E50 (Ver. 5. High-Z tRFC Auto Bank 0 Refresh Active 45 EDD1232AABH Bank 0 Read VIH or VIL ...
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... Self Refresh Cycle /CK CK tIS CKE /CS /RAS /CAS /WE BA Address A8=1 DM DQS DQ (output) DQ (input) tRP Precharge Self If needed refresh entry Data Sheet E0533E50 (Ver. 5.0) tIH CKE = low High-Z tSNR tSRD Self refresh Bank 0 exit Active 46 EDD1232AABH Bank 0 Read VIH or VIL ...
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... Package Drawing 144-ball FBGA Solder ball: Lead free (Sn-Ag-Cu 0.10 S INDEX MARK Data Sheet E0533E50 (Ver. 5.0) 12.00 ± 0.10 INDEX MARK 0.20 S 1.40 max S 0.35 ± 0.05 A 8.80 B 0.40 0.80 144 − φ0.45 ± 0. ECA-TS2-0131-01 47 EDD1232AABH Unit: mm ...
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... Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDD1232AABH. Type of Surface Mount Device EDD1232AABH: 144-ball FBGA < Lead free (Sn-Ag-Cu) > Data Sheet E0533E50 (Ver. 5.0) EDD1232AABH 48 ...
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... Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. Data Sheet E0533E50 (Ver. 5.0) EDD1232AABH 49 CME0107 ...
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... If these products/technology are sold, leased, or transferred to a third party third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Data Sheet E0533E50 (Ver. 5.0) EDD1232AABH 50 M01E0107 ...