EDD1232AABH ELPIDA [Elpida Memory], EDD1232AABH Datasheet - Page 25

• Manufacturer Part Number: EDD1232AABH
• Description: 128M bits DDR SDRAM (4M words x 32 bits)
• Manufacturer: ELPIDA [Elpida Memory]

Write operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4,
or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by
the column address, the bank select address which are loaded via the A0 to A11, BA0 to BA1 pins in the cycle when
the write command is issued. DQS should be input as the strobe for the input-data and DM as well during burst
operation. tWPREH prior to the first rising edge of the DQS should be set to Low and tWPST after the last falling
edge of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last
low period of DQS is referred as write postamble.
Data Sheet E0533E50 (Ver. 5.0)
Command
DQS
DQ
CL = 2.5
Address
CL = 2
CL = 3
/CK
CK
Command
DQS
DQS
DQS
/CK
NOP
DQ
DQ
DQ
CK
t0
READ
Row
ACT
t1
t0
BL = 2
BL = 4
BL = 8
tRCDWR
NOP
t0.5
tRPRE
Read Operation (/CAS Latency)
tAC,tDQSCK
t1
tRPRE
tWPRES
Column
WRITE
t4
tAC,tDQSCK
t1.5
Write Operation
tRPRE
tWPREH
t4.5 t5
tAC,tDQSCK
t2
in0
in0
in0
25
out0
in1
in1
in1
t2.5
out0
NOP
out1
in2
in2
t6
t3
in3
in3
tWPST
out0
out2 out3
out1
t3.5
in4 in5
t7
out2
out1
NOP
t4
tRPST
in6
out3
out2
t8
t4.5
tRPST
in7
out3
t5
t9
EDD1232AABH
tRPST
BL: Burst length
t5.5
VTT
VTT
VTT
VTT
VTT
VTT