EDD1232ACBH ELPIDA [Elpida Memory], EDD1232ACBH Datasheet
EDD1232ACBH
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EDD1232ACBH Summary of contents
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... DDR SDRAM EDD1232ACBH (4M words 32 bits) Specifications Density: 128M bits Organization 1M words 32 bits 4 banks Package: 144-ball FBGA Lead-free (RoHS compliant) and Halogen-free Power supply: VDD, VDDQ 2.5V 0.125V/+0.2V Data rate: 400Mbps (max.) Four internal banks for concurrent operation Interface: SSTL_2 Burst lengths (BL ...
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... Power Supply, Interface A: 2.5V, SSTL_2 Data Sheet E1202E20 (Ver.2.0) Internal Data Rate JEDEC speed bin bits) banks Mbps (max.) (CL-tRCDRD-tRP 400 DDR400B (3-3-3) 2 EDD1232ACBH Package 144-ball FBGA Environment Code F: Lead Free (RoHS compliant) and Halogen Free Speed 5B: DDR400B (3-3-3) Package BH: FBGA Die Rev. ...
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... A2 A11 A9 A5 RFU (Top view) Pin name CK /CK CKE VREF VDD VSS VDDQ VSSQ RFU 3 EDD1232ACBH VSSQ DM3 DQS3 NC VDDQ DQ27 VSSQ DQ26 DQ25 VDD VDDQ DQ24 VDDQ DQ15 DQ14 VDDQ DQ13 DQ12 NC DM1 DQS1 VDDQ DQ11 DQ10 ...
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... CONTENTS Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Pin Configurations .........................................................................................................................................3 Electrical Specifications.................................................................................................................................5 Block Diagram .............................................................................................................................................11 Pin Function.................................................................................................................................................12 Command Operation ...................................................................................................................................14 Simplified State Diagram .............................................................................................................................21 Operation of the DDR SDRAM ....................................................................................................................22 Timing Waveforms.......................................................................................................................................42 Package Drawing ........................................................................................................................................48 Recommended Soldering Conditions..........................................................................................................49 Data Sheet E1202E20 (Ver.2.0) EDD1232ACBH 4 ...
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... Tstg –55 to +125 min. typ. 2.375 2 0.49 VDDQ 0.50 VDDQ VREF – 0.04 VREF VREF + 0.15 — –0.3 — –0.3 — 0.5 VDDQ 0.2V 0.5 VDDQ 0.36 — 5 EDD1232ACBH Unit Note max. Unit Notes 2 0.51 VDDQ V VREF + 0.04 V VDDQ + 0 VREF – 0. VDDQ + 0.3 ...
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... Input ≥ VDD – 0 Input ≤ 0.2 V 300 max. Unit Test condition 2 µA VDD ≥ VIN ≥ VSS 5 µA VDDQ ≥ VOUT ≥ VSS 6 EDD1232ACBH Notes Notes ...
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... EDD1232ACBH max. Unit Notes VOUT = 0.2V, Unit Notes ns 10 tCK tCK tCK ...
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... RU (tWR/tCK) + tDAL — RU (tRP/tCK) tWTR 2 — tREFI — 7.8 8 EDD1232ACBH Unit Notes tCK tCK tCK µs ...
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... VTT VREF VIH (AC) VREF 0.31 VIL (AC) VREF 0.31 VID (AC) 0.62 VIX (AC) VREF SLEW 1 tCK tCL tCH VIX VDD VIH VREF VIL VSS t SLEW = (VIH (AC) – VIL (AC))/ t VTT 30pF Input Waveforms and Output Load 9 EDD1232ACBH Unit V/ns VDD VREF VSS ...
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... EDD1232ACBH 7.5ns min. max. Unit 1 + BL/2 + tCK tWR BL/2 tCK 1 + BL/2 + tCK tWTR 3 tCK 3 3 tCK 3 + BL/2 tCK 3 3 tCK 1 1 tCK 2 tCK 0 0 tCK 8 tCK ...
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... Data Sheet E1202E20 (Ver.2.0) Bank 1 Row address Memory cell array buffer Bank 0 and refresh counter Sense amp. Column decoder Column address buffer and burst Data control circuit counter Latch circuit DLL CK, /CK Input & Output buffer DQ 11 EDD1232ACBH Bank 3 Bank 2 DQS DM ...
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... BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table] BA0 Bank 0 L Bank 1 H Bank 2 L Bank 3 H Remark: H: VIH. L: VIL. Data Sheet E1202E20 (Ver.2.0) EDD1232ACBH Column address AY0 to AY7 BA1 ...
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... DM3 VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. Data Sheet E1202E20 (Ver.2.0) EDD1232ACBH DQs DQ0 to DQ7 DQ8 to DQ15 DQ16 to DQ23 DQ24 to DQ31 ...
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... L H PRE PALL REF SELF MRS EMRS EDD1232ACBH BA1 BA0 AP Address ...
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... Power down Power down exit (PDEX) Remark: H: VIH. L: VIL. : VIH or VIL. Notes: 1. All the banks must be in IDLE before executing this command. 2. The CKE level must be kept for 1 CK cycle at least. Data Sheet E1202E20 (Ver.2.0) EDD1232ACBH BA1 CKE n – 1 ...
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... ILLEGAL DESL NOP NOP NOP BST ILLEGAL BA, CA, A8 READ/READA Starting read operation Read/READA BA, CA, A8 WRIT/WRITA Starting write operation BA, RA ACT ILLEGAL* BA, A8 PRE, PALL Pre-charge ILLEGAL 16 EDD1232ACBH Next state ldle ldle 11 — 11 — 11 — 11 — ldle — ldle ldle 11 — 11 — 11 — ...
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... NOP NOP NOP BST ILLEGAL BA, CA, A8 READ/READA Starting read operation. Read/ReadA Starting new write BA, CA, A8 WRIT/WRITA operation. BA, RA ACT ILLEGAL* BA, A8 PRE/PALL ILLEGAL* ILLEGAL 17 EDD1232ACBH Next state Active Active Active Active 13 — 11 — Precharging — Precharging Precharging — 14 — 14 — 11, 14 — ...
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... READ/READA ILLEGAL* BA, CA, A8 WRIT/WRIT A ILLEGAL* BA, RA ACT ILLEGAL* BA, A8 PRE, PALL ILLEGAL* ILLEGAL Minimum delay (Concurrent AP supported) BL/2 CL(rounded up)+ (BL/ (BL/2) + tWTR BL EDD1232ACBH Next state Precharging Precharging — 14 — 14 — 11, 14 — 11, 14 — — Units tCK tCK tCK tCK tCK tCK ...
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... OPCODE Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table H Refer to operations in Function Truth Table L H Self refresh L L OPCODE Refer to operations in Function Truth Table Power down Refer to operations in Function Truth Table Power down 19 EDD1232ACBH Notes Idle ...
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... To issue read command, tSRD has to be satisfied to adjust DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command within 7.8 s. Power down exit [PDEX] The DDR SDRAM can exit from power down mode tPDEX after the cycle when [PDEX] is issued. Data Sheet E1202E20 (Ver.2.0) EDD1232ACBH 20 ...
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... Data Sheet E1202E20 (Ver.2.0) SELF REFRESH SR ENTRY SR EXIT *1 MRS REFRESH AUTO IDLE REFRESH CKE CKE_ IDLE ACTIVE POWER CKE_ DOWN CKE ROW ACTIVE BST READ WRITE READ Read WITH WITH AP AP READ READ READ WITH AP READ WITH AP PRECHARGE READA PRECHARGE PRECHARGE PRECHARGE 21 EDD1232ACBH ...
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... REF REF RFC 200 cycles (min LMODE BT A3 Burst Type Sequential 1 Interleave 22 EDD1232ACBH (9) Any MRS command t 2 cycles (min.) RFC Disable DLL reset with A8 = Low Burst Length BT=0 BT ...
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... EDD1232ACBH A1 A0 DLL A0 DLL Control 0 DLL Enable 1 DLL Disable Interleave ...
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... Data Sheet E1202E20 (Ver.2.0) tCK + tAC (ns) after the clock rising READ NOP Column tRPRE out0 out1 out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 Read Operation (Burst Length) 24 EDD1232ACBH t11 t9 t10 tRPST BL: Burst length ...
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... Read Operation (/CAS Latency WRITE NOP Column tWPREH tWPRES in0 in1 tWPST in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 Write Operation 25 EDD1232ACBH t4.5 t5 t5.5 tRPST VTT VTT out2 out3 t8 t9 in6 in7 BL: Burst length ...
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... High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed. t0 t0.5 CK /CK READ Command DQS Burst Stop during a Read Operation Data Sheet E1202E20 (Ver.2.0) t1 t1.5 t2 t2.5 t3 t3.5 t4 BST NOP tBSTZ out0 out1 26 EDD1232ACBH t4.5 t5 t5.5 3 cycles CL: /CAS latency ...
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... Note: Internal auto-precharge starts at the timing indicated by " Data Sheet E1202E20 (Ver.2.0) Refer to ‘Function truth table and related tRPD BL/2 cycles READA NOP tAC,tDQSCK out0 out1 out2 ". Read with auto-precharge NOP 1 + BL/2 + tWR cycles in1 in2 in3 in4 ". Burst Write ( EDD1232ACBH tRP (min) ACT out3 tRP ACT ...
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... ACT command. tRCDRD after the ACT command, the consecutive read command can be issued NOP READ Column B out out out Column = A Column = B Read Read Column = A Dout 28 EDD1232ACBH t9 t10 t11 out out out Column = B Dout Bank0 ...
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... Active READ to READ Command Interval (different bank) Data Sheet E1202E20 (Ver.2. READ READ NOP Column A Column B Column = A Column = B Read Read Bank0 Bank3 Read Read 29 EDD1232ACBH t8 t9 t10 t11 NOP out out out out out out Bank0 Bank3 ...
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... Precharge the bank without interrupting the preceding write operation. tRP after the precharge command, issue the ACT command. tRCDWR after the ACT command, the consecutive write command can be issued. tn+1 tn+2 tn+3 tn+4 WRIT Column B inA0 inA1 inB0 inB1 inB2 inB3 Column = A Column = B Write Write 30 EDD1232ACBH tn+5 tn+6 NOP Bank0 ...
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... ACT NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active WRITE to WRITE Command Interval (different bank) Data Sheet E1202E20 (Ver.2.0) tn tn+1 tn+2 NOP WRIT WRIT Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Bank3 Write Write 31 EDD1232ACBH tn+3 tn+4 tn+5 NOP Bank0, 3 ...
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... Precharge the bank independently of the preceding read operation. tRP after the precharge command, issue the ACT command. tRCDWR after the ACT command, the consecutive write command can be issued NOP WRIT tBSTZ (= CL) out0 out1 in0 in1 OUTPUT READ to WRITE Command Interval 32 EDD1232ACBH NOP in2 in3 INPUT ...
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... Precharge the bank independently of the preceding write operation. tRP after the precharge command, issue the ACT command. tRCDRD after the ACT command, the consecutive read command can be issued NOP READ tWTR* in3 WRITE to READ Command Interval 33 EDD1232ACBH NOP out0 out1 out2 OUTPUT ...
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... DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command not necessary. 1 — NOP CL=3 out0 out1 out2 out3 in2 34 EDD1232ACBH High-Z High ...
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... Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. [WRITE to READ delay = 4 clock cycle] Data Sheet E1202E20 (Ver.2. NOP CL=3 in2 in3 out0 out1 out2 out3 READ CL=3 tWTR* in3 35 EDD1232ACBH High-Z High NOP out0 out1 out2 out3 ...
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... NOP READ DQ DQS READ to PRECHARGE Command Interval (same bank): To Stop Output Data ( Data Sheet E1202E20 (Ver.2. PRE/ NOP PALL out0 out1 out2 out3 PRE/PALL NOP out0 out1 tHZP 36 EDD1232ACBH High-Z High-Z ...
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... Command WRIT DM DQS DQ in0 in1 Precharge Termination in Write Cycles (same bank) ( Data Sheet E1202E20 (Ver.2. NOP tWPD tWR in2 in3 Last data input NOP PRE/PALL tWR in2 in3 Data masked 37 EDD1232ACBH t6 t7 PRE/PALL NOP t6 t7 NOP ...
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... ACT command, the next ACT command can be issued. ACT NOP PRE ROW: 1 Bank3 Bank0 Active Precharge tRC Bank Active to Bank Active NOP ACT BS and ROW Bank3 Active tMRD 38 EDD1232ACBH NOP ACT NOP ROW: 0 Bank0 Active NOP ...
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... DM can mask input data. By setting DM to Low, data can be written. When DM is set to high, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function DQS DQ DM Data Sheet E1202E20 (Ver.2. Mask Mask Write mask latency = 0 DM Control 39 EDD1232ACBH t5 t6 ...
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... Refresh command is 9 Burst refreshing or posting by the DRAM controller greater than 8 refresh cycles is not allowed /CK CK VIH ≥ tRP CKE Command PRE NOP Data Sheet E1202E20 (Ver.2. ≥ tRFC REF REF Auto-Refresh 40 EDD1232ACBH tREFI. ≥ tRFC Any NOP Command ...
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... Data Sheet E1202E20 (Ver.2. tRP* tIS tIS tIS tIH NOP SELF Self-Refresh 41 EDD1232ACBH tn ≥ tSNR* 3 ≥ tSRD* 2 NOP Valid NOP ...
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... Data Sheet E1202E20 (Ver.2.0) tIS tIH tIS tIH tDQSCK tDQSCK tDQSCK tDQSQ tQH tLZ tAC tAC tDQSQ tQH tDSS tDSH tDQSL tDQSH tDIPW tDH tDH tDIPW 42 EDD1232ACBH VREF VREF tDQSCK tRPST tDQSQ tQH tAC tHZ tDQSQ tQH tDSS VREF tWPST VREF VREF tDIPW ...
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... Bank 0 Bank 0 Bank 0 Read Read Precharge 43 EDD1232ACBH tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tRPST Bank0 Access = VIH or VIL ...
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... Data Sheet E1202E20 (Ver.2.0) tRC tRAS tDQSS tDQSL tWPST tDQSH tDS tDS tDS tDH tWR tDH 44 EDD1232ACBH tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH ...
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... Data Sheet E1202E20 (Ver.2. tMRD Bank 3 Bank 3 Bank 3 Read Precharge Active R:b C tRWD Bank 3 Bank 3 Active Write 45 EDD1232ACBH VIH or VIL C:b'' b’’ tWRD Bank 3 Read Read cycle =VIH or VIL ...
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... Auto-Refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A8=1 DM DQS DQ (output) DQ (input) tRP Precharge If needed Data Sheet E1202E20 (Ver.2. High-Z tRFC Auto Bank 0 Refresh Active 46 EDD1232ACBH Bank 0 Read VIH or VIL ...
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... Self-Refresh Cycle /CK CK tIS CKE /CS /RAS /CAS /WE BA Address A8=1 DM DQS DQ (output) DQ (input) tRP Precharge Self If needed refresh entry Data Sheet E1202E20 (Ver.2.0) tIH CKE = low High-Z tSNR tSRD Self refresh Bank 0 exit Active 47 EDD1232ACBH Bank 0 Read VIH or VIL ...
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... Package Drawing 144-ball FBGA Solder ball: Lead free (Sn-Ag-Cu) 0.20 0. INDEX MARK Data Sheet E1202E20 (Ver.2.0) 10.5 ± 0.10 0. INDEX MARK S B 0.20 S 1.20 max S 0.35 ± 0.05 A 144 − φ0.45 ± 0.05 0.40 0.80 8.80 48 EDD1232ACBH Unit: mm φ0. ECA-TS2-0260-01 ...
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... Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDD1232ACBH. Type of Surface Mount Device EDD1232ACBH: 144-ball FBGA < Lead free (Sn-Ag-Cu) > Data Sheet E1202E20 (Ver.2.0) EDD1232ACBH 49 ...
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... Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. Data Sheet E1202E20 (Ver.2.0) EDD1232ACBH 50 CME0107 ...
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... If these products/technology are sold, leased, or transferred to a third party third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Data Sheet E1202E20 (Ver.2.0) EDD1232ACBH ...