EDD1232ACBH ELPIDA [Elpida Memory], EDD1232ACBH Datasheet - Page 30

• Manufacturer Part Number: EDD1232ACBH
• Description: 128M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

A Write Command to the Consecutive Write Command Interval
1. Same
2. Same
3. Different
Data Sheet E1202E20 (Ver.2.0)
Command
Destination row of the consecutive write
command
Bank
address
Address
DQS
/CK
DQ
CK
BA
Row address State
Same
Different
Any
ACT
Row
Bank0
Active
WRITE to WRITE Command Interval (same ROW address in the same bank)
t0
NOP
ACTIVE
—
ACTIVE
IDLE
Column A
WRIT
tn
Operation
The consecutive write can be performed after an interval of no less than 1 cycle to
interrupt the preceding write operation.
Precharge the bank to interrupt the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCDWR after the ACT command,
the consecutive write command can be issued. See ‘A write command to the
consecutive precharge interval’ section.
The consecutive write can be performed after an interval of no less than 1 cycle to
interrupt the preceding write operation.
Precharge the bank without interrupting the preceding write operation. tRP after
the precharge command, issue the ACT command. tRCDWR after the ACT
command, the consecutive write command can be issued.
Column B
Column = A
Write
WRIT
inA0 inA1 inB0 inB1 inB2 inB3
tn+1
30
tn+2
Column = B
Write
tn+3
tn+4
NOP
tn+5
EDD1232ACBH
tn+6
BL = 4
Bank0