EDD1232ACBH ELPIDA [Elpida Memory], EDD1232ACBH Datasheet - Page 34

• Manufacturer Part Number: EDD1232ACBH
• Description: 128M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

A Write command to the Consecutive Read Command Interval: To Interrupt the Write Operation
1. Same
2. Same
3. Different
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write
WRITE to READ Command Interval (Same bank, same ROW address)
Data Sheet E1202E20 (Ver.2.0)
Command
Destination row of the consecutive read
command
Bank
address
DQS
/CK
DM
DQ
CK
operation in this case.
Row address State
Same
Different
Any
WRIT
t0
1 cycle
READ
ACTIVE
—
ACTIVE
IDLE
in0
Data masked
t1
in1
[WRITE to READ delay = 1 clock cycle]
in2
t2
Operation
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
—*
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
—*
1
1
CL=3
t3
34
t4
out0 out1 out2 out3
t5
NOP
t6
EDD1232ACBH
t7
High-Z
High-Z
t8
BL = 4
CL = 3