EDD2516AKTA-7A ELPIDA [Elpida Memory], EDD2516AKTA-7A Datasheet

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... DDR SDRAM EDD2516AKTA (16M words × 16 bits) Description The EDD2516AKTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 4,194,304 words × 16 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high- speed data transfer is realized by the 2 bits prefetch- pipelined architecture ...

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... Ordering Information Mask Organization (words × bits) Part number version EDD2516AKTA-6B 16M × 16 EDD2516AKTA-7A K EDD2516AKTA-7B Part Number Elpida Memory Type D: Monolithic Device Product Family D: DDR SDRAM Density / Bank 25: 256M / 4-bank Organization 16: x16 Power Supply, Interface A: 2.5V, SSTL_2 Die Rev. Package TA: TSOP (II) Speed 6B: DDR333B (2 ...

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... CONTENTS Description .................................................................................................................................................... 1 Features ........................................................................................................................................................ 1 Pin Configurations......................................................................................................................................... 1 Ordering Information ..................................................................................................................................... 2 Part Number.................................................................................................................................................. 2 Electrical Specifications ................................................................................................................................ 4 Block Diagram............................................................................................................................................. 10 Pin Function ................................................................................................................................................ 11 Command Operation................................................................................................................................... 13 Simplified State Diagram ............................................................................................................................ 20 Operation of the DDR SDRAM ................................................................................................................... 21 Timing Waveforms ...................................................................................................................................... 40 Package Drawing........................................................................................................................................ 46 Recommended Soldering Conditions ......................................................................................................... 47 Preliminary Data Sheet E0303E40 (Ver. 4.0) EDD2516AKTA 3 ...

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... Tstg –55 to +125 min. typ. 2.3 2 0.49 × VDDQ 0.50 × VDDQ VREF – 0.04 VREF VREF + 0.15 — –0.3 — –0.3 — 0.5 × VDDQ − 0.2V 0.5 × VDDQ 0.36 — 4 EDD2516AKTA Unit Note °C °C max. Unit Notes 2 0.51 × VDDQ V VREF + 0.04 V VDDQ + 0 VREF – ...

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... Unit –2 2 µA –5 5 µA –15.2 — mA 15.2 — EDD2516AKTA Test condition Notes CKE ≥ VIH tRC = tRC (min.) CKE ≥ VIH 2. tRC = tRC (min.) CKE ≤ VIL 4 CKE ≥ VIH, /CS ≥ VIH 4, 5 DQ, DQS VREF CKE ≥ ...

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... EDD2516AKTA max. Unit Notes -7B min. max. Unit Notes 7 0.45 0.55 tCK 0.45 0.55 tCK min — tCK (tCH, tCL) – ...

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... EDD2516AKTA -7B min. max. Unit Notes 0.9 — 0.9 — 2.2 — — tCK 45 120000 ns 67.5 — — — ...

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... VIH (AC) VREF − 0.31 VIL (AC) VID (AC) 0.62 VIX (AC) VREF SLEW 1 tCK tCL tCH VIX VDD VIH VREF VIL VSS Δt SLEW = (VIH (AC) – VIL (AC))/Δt VTT RT = 50Ω 30pF Input Waveforms and Output Load 8 EDD2516AKTA Unit V/ns VDD VREF VSS ...

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... EDD2516AKTA 7.5ns min. max. Unit 3 + BL/2 — tCK BL/2 — tCK 2 + BL/2 — tCK 2 — tCK 3 — tCK 2 2 tCK 2.5 2.5 tCK 2 + BL/2 — tCK 3 + BL/2 — ...

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... Preliminary Data Sheet E0303E40 (Ver. 4.0) Bank 1 Row address Memory cell array buffer Bank 0 and refresh counter Sense amp. Column decoder Column address buffer and burst Data control circuit counter Latch circuit DLL Input & Output buffer CK, / EDD2516AKTA Bank 3 Bank 2 DQS DM ...

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... BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table] Bank 0 Bank 1 Bank 2 Bank 3 Remark: H: VIH. L: VIL. Preliminary Data Sheet E0303E40 (Ver. 4.0) Column address AY0 to AY8 BA0 EDD2516AKTA BA1 ...

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... DQ7) data strobe signal, UDQS is the upper byte (DQ8 to DQ15) data strobe signal. VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. Preliminary Data Sheet E0303E40 (Ver. 4.0) EDD2516AKTA 12 ...

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... PALL REF SELF MRS EMRS EDD2516AKTA Address × × × × × × × × × H × × × × ...

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... × × × EDD2516AKTA BA1 /CAS /WE Address Notes × × × × × × × × × × × × ...

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... DESL × H NOP × L BST H BA, CA, A10 READ/READA L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE, PALL × × 15 EDD2516AKTA Operation Next state NOP ldle NOP ldle 11 ILLEGAL* — 11 ILLEGAL* — 11 ILLEGAL* — 11 ILLEGAL* — NOP ldle ILLEGAL — NOP ...

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... H NOP × L BST H BA, CA, A10 READ/READA L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE/PALL × × 16 EDD2516AKTA Operation Next state NOP Active NOP Active BST Active Interrupting burst read operation to Active start new read 13 ILLEGAL* — 11 ILLEGAL* — Interrupting burst read operation to ...

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... READ/READA L BA, CA, A10 WRIT/WRIT A H BA, RA ACT L BA, A10 PRE, PALL × × Minimum delay (Concurrent AP supported) BL/2 CL(rounded up)+ (BL/ (BL/2) + tWTR BL EDD2516AKTA Operation Next state NOP Precharging NOP Precharging ILLEGAL — 14 ILLEGAL* — 14 ILLEGAL* — 11, 14 ILLEGAL* — 11, 14 ILLEGAL* — ...

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... L H Refer to operations in Function Truth Table × Self refresh OPCODE Refer to operations in Function Truth Table × × × × Power down × × × × Refer to operations in Function Truth Table × × × × Power down 18 EDD2516AKTA Notes ...

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... DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command within 7.8 μs. Power down exit [PDEX] The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued. Preliminary Data Sheet E0303E40 (Ver. 4.0) EDD2516AKTA 19 ...

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... SELF REFRESH SR ENTRY SR EXIT *1 MRS REFRESH AUTO IDLE REFRESH CKE CKE_ IDLE ACTIVE POWER CKE_ DOWN CKE ROW ACTIVE BST WRITE READ WRITE READ Read WITH WITH AP AP READ READ READ WITH AP READ WITH AP PRECHARGE READA PRECHARGE PRECHARGE PRECHARGE PRECHARGE 20 EDD2516AKTA ...

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... LMODE BT A3 Burst Type Sequential 2 Interleave 21 EDD2516AKTA (9) Any REF MRS command t 2 cycles (min.) RFC Disable DLL reset with A8 = Low Burst Length BT=0 BT ...

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... EDD2516AKTA DLL A0 DLL Control 0 DLL Enable 1 DLL Disable Interleave ...

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... NOP Address Row DQS Preliminary Data Sheet E0303E40 (Ver. 4. READ NOP Column tRPRE out0 out1 out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 Read Operation (Burst Length) 23 EDD2516AKTA tRPST BL: Burst length ...

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... Read Operation (/CAS Latency) tn tn+0.5 tn+1 tn+2 tn+3 WRITE Column tWPRE tWPRES in0 in1 tWPST in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 Write Operation 24 EDD2516AKTA t4 t4.5 t5 t5.5 tRPST VTT VTT tRPST VTT VTT out3 tn+4 tn+5 NOP in6 in7 BL: Burst length ...

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... High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed /CK READ Command DQS DQS CL = 2.5 DQ Preliminary Data Sheet E0303E40 (Ver. 4.0) t0.5 t1 t1.5 t2 t2.5 t3 t3.5 BST NOP tBSTZ 2 cycles out0 out1 tBSTZ out0 out1 Burst Stop during a Read Operation 25 EDD2516AKTA t4 t4.5 t5 t5.5 2.5 cycles CL: /CAS latency ...

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... Note: Internal auto-precharge starts at the timing indicated by " Preliminary Data Sheet E0303E40 (Ver. 4.0) Refer to ‘Function truth table and related tRPD 2 cycles (= BL/2) READA NOP tAC,tDQSCK out0 out1 out2 ". Read with auto-precharge NOP BL cycles in1 in2 in3 in4 ". Burst Write ( EDD2516AKTA tRP (min) ACT out3 tRP ACT ...

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... ACT command. tRCD after the ACT command, the consecutive read command can be issued READ READ Column A Column B out out out Column = B Read Column = A Dout 27 EDD2516AKTA NOP out out out Column = B Dout Bank0 ...

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... READ to READ Command Interval (different bank) Preliminary Data Sheet E0303E40 (Ver. 4. READ READ NOP Column A Column B out out A0 A1 Column = A Column = B Read Read Bank0 Dout Bank0 Bank3 Read Read 28 EDD2516AKTA NOP out out out out Bank3 Dout ...

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... Precharge the bank without interrupting the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. tn tn+1 tn+2 tn+3 WRIT Column B inA0 inA1 inB0 inB1 inB2 inB3 Column = A Column = B Write Write 29 EDD2516AKTA tn+4 tn+5 tn+6 NOP Bank0 ...

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... NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active WRITE to WRITE Command Interval (different bank) Preliminary Data Sheet E0303E40 (Ver. 4.0) tn tn+1 tn+2 NOP WRIT WRIT Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Bank3 Write Write 30 EDD2516AKTA tn+3 tn+4 tn+5 NOP Bank0, 3 ...

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... Precharge the bank independently of the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued NOP WRIT out0 out1 in0 in1 in2 INPUT READ to WRITE Command Interval 31 EDD2516AKTA NOP in3 ...

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... Precharge the bank independently of the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued NOP READ tWRD (min) tWTR* BL cycle in1 in2 in3 INPUT WRITE to READ Command Interval 32 EDD2516AKTA t5 t6 NOP out2 out0 out1 OUTPUT ...

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... DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command not necessary. 1 — NOP out0 out1 out2 out3 in2 33 EDD2516AKTA High-Z High CL= 2 ...

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... READ delay = 3 clock cycle] Preliminary Data Sheet E0303E40 (Ver. 4. READ NOP CL=2 in2 in3 out0 out1 out2 out3 READ CL=2 tWTR* out0 out1 out2 out3 in2 in3 Data masked 34 EDD2516AKTA High-Z High CL NOP CL= 2 ...

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... NOP NOP READ DQ DQS tRPD = BL/2 READ to PRECHARGE Command Interval (same bank): To output all data ( Preliminary Data Sheet E0303E40 (Ver. 4. PRE/ NOP PALL out0 out1 out2 out3 PRE/ NOP PALL out0 out1 out2 out3 35 EDD2516AKTA ...

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... Command NOP READ DQ DQS READ to PRECHARGE Command Interval (same bank): To stop output data ( Preliminary Data Sheet E0303E40 (Ver. 4. PRE/PALL out0 out1 tHZP PRE/PALL CL = 2.5 out0 out1 tHZP 36 EDD2516AKTA NOP High-Z High NOP High-Z High-Z ...

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... Command WRIT DM DQS DQ in0 Precharge Termination in Write Cycles (same bank) ( Preliminary Data Sheet E0303E40 (Ver. 4. NOP tWPD tWR in1 in2 in3 Last data input PRE/PALL NOP tWR in1 in2 in3 Data masked 37 EDD2516AKTA PRE/PALL NOP NOP ...

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... ACT command, the next ACT command can be issued. ACT NOP PRE ROW: 1 Bank3 Bank0 Active Precharge tRC Bank Active to Bank Active MRS NOP ACT BS and ROW Bank3 Active tMRD 38 EDD2516AKTA NOP ACT NOP ROW: 0 Bank0 Active NOP ...

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... By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function DQS DQ DM Preliminary Data Sheet E0303E40 (Ver. 4. Mask Mask Write mask latency = 0 DM Control 39 EDD2516AKTA t5 t6 ...

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... Preliminary Data Sheet E0303E40 (Ver. 4.0) tIS tIH tIS tIH tDQSCK tDQSCK tDQSCK tDQSQ tQH tLZ tAC tAC tDQSQ tQH tDSS tDSH tDQSL tDQSH tDIPW tDH tDH tDIPW 40 EDD2516AKTA VREF VREF tDQSCK tRPST tDQSQ tQH tAC tHZ tDQSQ tQH tDSS VREF tWPST VREF VREF tDIPW ...

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... Bank 0 Bank 0 Bank 0 Read Read Precharge 41 EDD2516AKTA tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tRPST Bank0 Access = VIH or VIL ...

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... Preliminary Data Sheet E0303E40 (Ver. 4.0) tRC tRAS tDQSS tDQSL tWPST tDQSH tDS tDS tDS tDH tWR tDH 42 EDD2516AKTA tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH ...

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... tMRD Bank 3 Mode Bank 3 Read register Active set R:b C:b a tRWD Bank 3 Bank 3 Active Write 43 EDD2516AKTA Bank Precharge VIH or VIL C:b'' b’’ b tWRD Bank 3 Read Read cycle =VIH or VIL ...

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... Auto Refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge If needed Preliminary Data Sheet E0303E40 (Ver. 4.0) High-Z tRFC Auto Bank 0 Refresh Active 44 EDD2516AKTA Bank 0 Read VIH or VIL ...

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... CK CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge Self If needed refresh entry Preliminary Data Sheet E0303E40 (Ver. 4.0) tIS tIH CKE = low High-Z Self refresh exit 45 EDD2516AKTA tSNR tSRD Bank 0 Bank 0 Active Read VIH or VIL ...

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... 0.91 max. 0. Note: This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.20mm per side. Preliminary Data Sheet E0303E40 (Ver. 4. 8° 46 EDD2516AKTA Unit: mm 0.80 Nom 0.25 +0.15 0.60 −0.20 ECA-TS2-0143-01 ...

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... Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDD2516AKTA. Type of Surface Mount Device EDD2516AKTA: 66-pin Plastic TSOP (II) Preliminary Data Sheet E0303E40 (Ver. 4.0) EDD2516AKTA 47 ...

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... Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. Preliminary Data Sheet E0303E40 (Ver. 4.0) NOTES FOR CMOS DEVICES 48 EDD2516AKTA CME0107 ...

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... If these products/technology are sold, leased, or transferred to a third party third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Preliminary Data Sheet E0303E40 (Ver. 4.0) EDD2516AKTA 49 M01E0107 ...