EDD2516AKTA-7A ELPIDA [Elpida Memory], EDD2516AKTA-7A Datasheet - Page 33

• Manufacturer Part Number: EDD2516AKTA-7A
• Description: 256M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

A Write command to the consecutive Read command interval: To interrupt the write operation
1. Same
2. Same
3. Different
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write
WRITE to READ Command Interval (Same bank, same ROW address)
Preliminary Data Sheet E0303E40 (Ver. 4.0)
Command
Destination row of the consecutive read
command
Bank
address
DQS
/CK
DM
DQ
CK
operation in this case.
Row address State
Same
Different
Any
WRIT
t0
1 cycle
READ
ACTIVE
—
ACTIVE
IDLE
in0
Data masked
t1
in1
CL=2
[WRITE to READ delay = 1 clock cycle]
in2
t2
Operation
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
—*
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
—*
1
1
t3
out0 out1 out2 out3
33
t4
t5
NOP
t6
High-Z
High-Z
EDD2516AKTA
t7
t8
BL = 4
CL= 2